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McBSP Integration
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NOTE:
When the McBSP2 module does not require the functional clock anymore, the software can
disable it at the PRCM level by setting the EN_MCBSP2 bit (PRCM.CM_FCLKEN_PER[0]) in
the PRCM registers. The clock is effectively cut, provided the other modules that receive it
do not require it. For more details, see
, Power Reset and Clock Management.
At PRCM level, when all the conditions to shut-off PER_96M_FCLK clock are met the PRCM
automatically launches a hardware handshake protocol to ensure McBSP2 is ready to have
this clock switched off. Namely, the PRCM asserts an idle request to McBSP2. For more
details, see
, Power Reset and Clock Management.
Only, the CLKX signal is connected by mcbsp2_clkx pads. The CLKR signal is connected to the CLKX
signal. These signals are used like functional clocks by the intermediary of the SRG.
•
The McBSP2_ICLK runs at the L4 core interconnect clock speed. It is used to trigger access to the
McBSP2 L4 interface and McBSP2 configuration interface via the MPU/IVA2.2 shared bus. It can also
be an input clock for the McBSP sample-rate generator (clock divider), depending on the module
configuration (see
). Its source is either the PER_L4_ICLK signal.
NOTE:
When the McBSP2 module does not require the interface clock anymore, the software can
disable it at the PRCM level by setting the EN_MCBSP2 bit (PRCM.CM_ICLKEN_PER[0]) in
the PRCM registers. The clock is effectively cut, provided the other modules that receive it
do not require it. For more information, see
, Power Reset and Clock Management.
At PRCM level, when all the conditions to shut-off PER_L4_ICLK clock are met the PRCM
automatically launches a hardware handshake protocol to ensure McBSP2 is ready to have
this clock switched off. Namely, the PRCM asserts an idle request to McBSP2. For more
details, see
, Power Reset and Clock Management.
It is also possible to activate an autoidle mode for this clock (PRCM.CM_AUTOIDLE_PER[0]
register AUTO_MCBSP2 bit set to 1). In this case, McBSP2_ICLK follows the CORE_L4
clock domain behavior on the device. For more information, see
, Power Reset and
Clock Management.
21.3.2.2.3 McBSP3 Clocks
The McBSP3 module is clocked by a functional clock (CLKS, CLKX or CLKR) and an interface clock
(McBSP3_ICLK).
•
The functional clock is used to generate control signals depending on the module internal configuration
(see
). For McBSP3 module, the functional clock comes from the CLKS signal CLKX
signal, or CLKR signal. The choice between these three clocks is defined by the SCLKME bit of the
MCBSP3.
[7] register and the CLKSM bit of the
[13] register.
The CLKS signal of the McBSP3 module is linked to an internal clock (PER_96M_FCLK) provided by
PRCM, whereas the CLKS signal can also be linked to an external signal through the mcbsp_clks pin
of the device boundary. The MCBSP3_CLKS bit of the CONTROL.CONTROL_DEVCONF1[0] register
is used to select the McBSP3 module CLKS signal source:
–
0: The CLKS source is from the PER_96M_FCLK.
–
1: The CLKS source is from the mcbsp_clks pin.
For more information, see
, System Control Module.
NOTE:
When the McBSP3 module does not require the functional clock anymore, the software can
disable it at the PRCM level by setting the EN_MCBSP3 bit (PRCM.CM_FCLKEN_PER[1]) in
the PRCM registers. The clock is effectively cut, provided the other modules that receive it
do not require it. For more details, see
, Power Reset and Clock Management.
At PRCM level, when all the conditions to shut-off PER_96M_FCLK clock are met the PRCM
automatically launches a hardware handshake protocol to ensure McBSP3 is ready to have
this clock switched off. Namely, the PRCM asserts an idle request to McBSP3. For more
details, see
, Power Reset and Clock Management.
3076
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
