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McBSP Basic Programming Model
21.5.1.5.2.2.7 Set the Receive Interrupt Mode
Please refer to
.
21.5.1.5.2.2.8 Set the Receive DMA Mode
The McBSP receive-data DMA requests (McBSPi_DMA_RX) are active after the
McBSPi.
[0] RRST bit is released. After reset, the default DMA threshold (and
length) is 1.
The receive DMA requests can be disabled by setting the McBSPi.
[3] RDMAEN
bit to 0. When disabling the DMA, the DMA request line is deasserted even if a DMA transfer is pending,
and the DMA state-machine is not reset.
To configure the McBSP receive data DMA requests, perform the following:
•
Write the receive McBSPi.
register with the required receive DMA request
length (the length of the transfer is the same as the threshold value + 1).
•
As long as the occupied locations level in the RB is above or equal to the THRSH1_REG value + 1,
the DMA request is asserted.
•
After transferring the configured (THRSH1_REG value + 1) number of words, the receive DMA request
is deasserted, and then reasserted as soon as the conditions are met again.
21.5.1.5.2.3 Frame-Sync Behavior
21.5.1.5.2.3.1 Set the Receive Frame-Sync Mode
McBSPi.
[15] GSYNC bit,
McBSPi.
[15] ALB bit and McBSPi.
[5] DLB bit field are
used to determine the source for receive frame synchronization and the function of the mcbsp_fsr pin.
below shows how you can select various sources to provide the receive
frame-synchronization signal and the effect on the mcbsp_fsr pin. The polarity of the signal on the
mcbsp_fsr pin is determined by the McBSPi.
[2] FSRP bit.
Table 21-29. FSRM and GSYNC Effects on Frame-Sync Signal and mcbsp_fsr Pin
FSRM
GSYNC
Source of Receive Frame Synchronization
MCBSPLP.FSR Pin Status
0
0 or 1
An external frame synchronization signal enters the
Input
McBSP module through the mcbsp_fsr pin. The signal
is then inverted as determined by FSRP bit before
being used as internal FSR.
1
0
Internal FSR is driven by the SRG
Output. FSG is inverted as determined by
frame-synchronization signal (FSG).
FSRP bit before being driven out on the
mcbsp_fsr pin.
1
1
Internal FSR is driven by the SRG
Input. The external frame-synchronization
frame-synchronization signal (FSG).
input on the mcbsp_fsr pin is used to
synchronize CLKG and generate FSG pulses.
In digital loop-back mode (DLB=1), the transmit frame-synchronization signal is used as the receive
frame-synchronization signal.
Also in the analog loop back mode (ALB=1), the internal receive clock signal (CLKR), and the internal
receive frame-synchronization signal (FSR) are internally connected to their transmit counterparts, CLKX
and FSX.
For more details on clock and frame-sync configuration, see
21.5.1.5.2.3.2 Set the Receive Frame-Sync Polarity
The McBSPi.
[2] FSRP bit determines whether frame-synchronization pulses are
active high or active low on the mcbsp_fsr pin.
3139
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated
