Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
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Table 3-436. PM_PWSTST_EMU
Address Offset 0x0000 00E4
Physical Address 0x4830 71E4 Instance EMU_PRM
Description This register provides a status on the power state transition of the EMULATION domain.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
INTRANSITION
POWERSTATEST
Bits Field Name Description Type Reset
31:21 RESERVED Write 0s for future compatibility. Read returns 0. R 0x000
20 INTRANSITION Domain transition status R 0x0
0x0: No transition
0x1: EMULATION power domain transition is in progress.
19:2 RESERVED Write 0x0040 for future compatibility. Read returns R 0x00040
0x0040.
1:0 POWERSTATEST Current power state status R 0x3
0x0: Power domain is OFF
0x1: Reserved
0x2: Reserved
0x3: Power domain is ON
Table 3-437. Register Call Summary for Register PM_PWSTST_EMU
PRCM Basic Programming Model
• PM_PWSTST_ <domain_name> (Power State Status Register) : [0]
PRCM Register Manual
• EMU_PRM Register Summary : [1]
3.8.2.13 Global_Reg_PRM Registers
3.8.2.13.1 Global_Reg_PRM Register Summary
Table 3-438. Global_Reg_PRM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
PRM_VC_SMPS_SA RW 32 0x0000 0020 0x4830 7220 W
PRM_VC_SMPS_VOL_RA RW 32 0x0000 0024 0x4830 7224 W
PRM_VC_SMPS_CMD_RA RW 32 0x0000 0028 0x4830 7228 W
PRM_VC_CMD_VAL_0 RW 32 0x0000 002C 0x4830 722C W
PRM_VC_CMD_VAL_1 RW 32 0x0000 0030 0x4830 7230 W
PRM_VC_CH_CONF RW 32 0x0000 0034 0x4830 7234 W
PRM_VC_I2C_CFG RW 32 0x0000 0038 0x4830 7238 W
PRM_VC_BYPASS_VAL RW 32 0x0000 003C 0x4830 723C W
PRM_RSTCTRL RW 32 0x0000 0050 0x4830 7250 C
PRM_RSTTIME RW 32 0x0000 0054 0x4830 7254 C
626 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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