Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Basic Programming Model
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NOTE: The L1 cache memory bank can be configured to be either entirely or partially cache or flat
memory. This configuration is done in the IVA2.2 subsystem. The part that is configured as
cache memory can be retained; however, because tag and validity bit information are not
retained in the case of L1 cache, this part cannot be retrieved after wakeup. It is important to
configure the L1 cache memory state with a consistent value depending on the chosen
configuration when the domain is in retention state:
•
If the L1 cache memory bank is entirely configured as cache memory, set the
PM_PWSTCTRL_IVA2 [8] SHAREDL1CACHEFLATRETSTATE bit to the same value as
the PM_PWSTCTRL_IVA2 [2] LOGICRETSTATE bit.
• If the L1 cache memory bank is entirely or partially configured as flat memory, set the
PM_PWSTCTRL_IVA2 [8] SHAREDL1CACHEFLATRETSTATE bit to the same value as
the PM_PWSTCTRL_IVA2 [9] L1FLATMEMRETSTATE bit.
The same mechanism applies to the L2 cache memory bank.
Because the L2 cache may not be useful in a system when the DSP frequency and interconnect
frequencies are in the same range, this memory bank can be switched off when the domain is on.
3.6.4.2 PM_PWSTST_ <domain_name> (Power State Status Register)
The power state status register provides the status of the power state transition of the domain.
This register holds the following bit fields:
• POWERSTATESTATUS: Indicates the current power state of the domain (on, retention, off)
• LOGICSTATESTATUS: Indicates the current logic power state
• MEMORYSTATESTATUS: Indicates the current memory power state
• INTRANSITION: Indicates an ongoing power state transition from ON power state to inactive, off, or
retention, and from inactive, off, or retention power states to on power state
The memory power state is updated by performing a dynamic memory change (the
PM_PWSTCTRL_<domain_name> MEMORYCHANGE bit). Software clears the
PM_PREPWST_<domain_name> register (this forces a memory change to the same value).
The device has the following power state status registers:
• PM_PWSTST_MPU : MPU domain power state status
• PM_PWSTST_CORE : CORE domain power state status
• PM_PWSTST_SGX : SGX domain power state status
• PM_PWSTST_DSS : DSS domain power state status
• PM_PWSTST_CAM : CAM domain power state status
• PM_PWSTST_PER : PER domain power state status
• PM_PWSTST_NEON : NEON domain power state status
• PM_PWSTST_EMU : EMU domain power state status
• PM_PWSTST_IVA2 : IVA2 domain power state status
• PM_PWSTST_USBHOST : USBHOST domain power state status
The MPU domain power state status register indicates the current domain, logic, L1 cache (on or off), and
L2 cache (on, retention, or off) power state.
The CORE domain power state status register indicates the current domain, logic (on or off), and memory
banks 1 and 2 (on, retention, or off) power state.
The SGX, DSS, CAM, PER, NEON, USBHOST, and EMU domain power state status registers indicate
the current domain (on, inactive, retention, or off) power state or that the power domain transition is in
progress. Because the SGX memory state is not programmable and reflects the power state, the SGX
power domain does not require a memory power state.
The IVA2 domain power state status register indicates the current domain (on, inactive, retention, or off),
logic (on or off), L1 cache and flat memory (on, retention, or off), L2 cache and flat memory (on, retention,
or off) power state status.
418 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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