Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 594 / 3738

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PRCM Register Manual
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
POWERSTATE MEMONSTATE
MEMRETSTATE
LOGICRETSTATE
Bits Field Name Description Type Reset
31:18 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000
17:16 MEMONSTATE Memory state when ON R 0x3
0x3: Memory is always ON when domain is ON.
15:9 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00
8 MEMRETSTATE Memory state when RETENTION R 0x1
0x1: Memory is always retained when domain is in
RETENTION state.
7:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00
2 LOGICRETSTATE Logic state when RETENTION R 0x1
0x1: Logic is always retained when domain is in
RETENTION state.
1:0 POWERSTATE Power state control RW 0x3
0x0: OFF state
0x1: RETENTION state
0x2: Reserved
0x3: ON state
Table 3-371. Register Call Summary for Register PM_PWSTCTRL_SGX
PRCM Basic Programming Model
• PM_PWSTCTRL_ <domain_name> (Power State Control Register) : [0]
PRCM Register Manual
• SGX_PRM Register Summary : [1]
Table 3-372. PM_PWSTST_SGX
Address Offset 0x0000 00E4
Physical Address 0x4830 6BE4 Instance SGX_PRM
Description This register provides a status on the power state transition of the SGX domain.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
INTRANSITION
POWERSTATEST
Bits Field Name Description Type Reset
31:21 RESERVED Read returns 0. R 0x000
20 INTRANSITION Domain transition status R 0x0
0x0: No transition
0x1: SGX power domain transition is in progress.
594 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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