Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 416 / 3738

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PRCM Basic Programming Model
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3.6.4 Power Management Registers
3.6.4.1 PM_PWSTCTRL_ <domain_name> (Power State Control Register)
The power state control register allows controlling the power state transition of the domain.
This register holds the following bit fields:
• POWERSTATE: Power state (ON, retention, or off) to be applied for the next transition
• LOGICRETSTATE: Logic is retained or switched off when the domain goes into retention. This feature
is domain-dependent and is not necessarily programmable (read only).
• MEMRETSTATE[1 to X]: Memory block i is retained (RAM state retained) or switched off (RAM state
not retained) when the domain goes into retention. This feature is domain-dependent and is not
necessarily programmable (read only).
• MEMONSTATE[1 to X]: Memory block i in the domain is on (RAM active), retained (RAM inactive but
state retained) or switched off (RAM state not retained) when the domain is on. This feature is
domain-dependent and is not necessarily programmable (read only).
• MEMORYCHANGE: Allows updating the memory state according to latest MEMONSSTATE[1 to X]
setting.
The device has the following power state control registers:
• PM_PWSTCTRL_MPU : MPU domain power management
• PM_PWSTCTRL_CORE : CORE domain power management
• PM_PWSTCTRL_SGX : SGX domain power management
• PM_PWSTCTRL_DSS : DSS domain power management
• PM_PWSTCTRL_CAM : CAM domain power management
• PM_PWSTCTRL_PER : PER domain power management
• PM_PWSTCTRL_NEON : NEON domain power management
• PM_PWSTCTRL_IVA2 : IVA2 domain power management
• PM_PWSTCTRL_USBHOST : USBHOST domain power management
MPU domain power management has the following features:
• The power state is programmable to on, retention, and off states.
• Logic and L1 cache state are switchable to off and retention states when the power domain is in
retention state.
• L2 cache state is switchable to off and retention states when the power domain is in retention state.
• L2 cache state is switchable to off and on states when the power domain is in on state.
• L2 cache state can be switched dynamically when the domain state is on (no power transition is
required).
• The L1 cache is always on when the power domain state is on.
CORE domain power management has the following features:
• The power state is programmable to on, retention, or off states.
• Nonretained logic is switchable to off and retention states when the power domain is in retention state.
• Memory bank 1 and 2 states are switchable to off and retention states when the power domain is in
retention state.
• Memory bank 1 and 2 states are switchable to off, retention, and on states when the power domain is
in on state.
• Memory bank 1 and 2 states can be switched dynamically when the domain state is on (no power
transition is required).
SGX domain power management has the following features:
• The power state is programmable to on, retention, and off states.
• The logic is always in retention state when the power domain is in retention state.
• The memory is always in retention state when the power domain is in retention state.
• The memory is always in on state when the power domain is in on state.
416 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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