Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 622 / 3738

Public Version
PRCM Register Manual
www.ti.com
Bits Field Name Description Type Reset
0 EN_CORE CORE domain dependency (CORE-L3 clock domain RW 0x1
only, not CORE-L4)
0x0: PER domain is independent of CORE domain
wake-up event (CORE-L3 clock domain only, not
CORE-L4).
0x1: PER domain is woken-up upon CORE domain
wake-up event.
Table 3-426. Register Call Summary for Register PM_WKDEP_PER
PRCM Functional Description
• Device Wake-Up Events : [0] [1] [2] [3]
PRCM Basic Programming Model
• PM_WKDEP_ <domain_name> (Wake-Up Dependency Register) : [4]
PRCM Register Manual
• PER_PRM Register Summary : [5]
Table 3-427. PM_PWSTCTRL_PER
Address Offset 0x0000 00E0
Physical Address 0x4830 70E0 Instance PER_PRM
Description This register controls the PER domain power state transition.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
POWERSTATE MEMONSTATE
MEMRETSTATE
LOGICRETSTATE
Bits Field Name Description Type Reset
31:18 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000
17:16 MEMONSTATE Memory state when ON R 0x3
0x3: Memory is always ON when domain is ON.
15:9 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00
8 MEMRETSTATE Memory state when RETENTION R 0x1
0x1: Memory is always retained when domain is in
RETENTION state.
7:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00
2 LOGICRETSTATE Logic state when domain is RETENTION RW 0x1
0x0: Logic build with retention flip-flop (GPIO) is retained
and remaining logic is OFF when domain is in
RETENTION state.
0x1: Logic is retained when domain is in RETENTION
state.
1:0 POWERSTATE Power state control RW 0x3
0x0: OFF state
0x1: RETENTION state
0x2: Reserved
0x3: ON state
622 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated