Texas Instruments OMAP36 Series, Technical Reference Manual

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Public Version
McBSP Register Manual
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Bits Field Name Description Type Reset
1 COEFFWREN Write enable FIR coefficients. RW 0x0
0x1:
If a 0 to 1 transition on this bit occurs, the write coefficient
index is reset. When this bit is 1, all coefficients can be
written in SFIRCR_REG performing 128 write accesses
with SIDETONEEN 1. First access writes coefficient
index 0
Read access in this case returns the last written value.
0x0:
If a 1 to 0 transition on this bit occurs, the read coefficient
index is reset. When this bit is 0, all coefficients can be
read from SFIRCR_REG by performing 128 read
accesses with SIDETONEEN 0. First access reads
coefficient index 0.
0 SIDETONEEN Sidetone mode enable. RW 0x0
0x0: Sidetone disabled
0x1: Sidetone enabled
Table 21-147. Register Call Summary for Register ST_SSELCR_REG
McBSP Functional Description
• Data Processing Path : [0]
• Data Processing : [1] [2] [3]
McBSP Basic Programming Model
• SIDETONE Activation Procedure : [4]
• SIDETONE Initialization Procedure : [5] [6]
• SIDETONE FIR Coefficients Writing : [7] [8]
• SIDETONE FIR Coefficients Reading : [9]
McBSP Register Manual
• SIDETONE Register Mapping Summary : [10] [11]
3208 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
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