Public Version
McBSP Register Manual
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Table 21-43. SIDETONE_McBSP3 Registers Mapping Summary (continued)
Register Name
Type
Register Width (Bits)
Address Offset
Physical Address
RW
32
0x0000 0018
0x4902 A018
RW
32
0x0000 001C
0x4902 A01C
RW
32
0x0000 0024
0x4902 A024
RW
32
0x0000 0028
0x4902 A028
RW
32
0x0000 002C
0x4902 A02C
21.6.3 McBSP Register Description
Table 21-44. MCBSPLP_DRR_REG
Address Offset
0x0000 0000
Physical Address
0x4807 4000
Instance
McBSP1
0x4809 6000
McBSP5
0x4902 2000
McBSP2
0x4902 4000
McBSP3
0x4902 6000
McBSP4
Description
McBSPLP data receive register
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DRR
Bits
Field Name
Description
Type
Reset
31:0
DRR
Data receive register
R
0x00000000
Table 21-45. Register Call Summary for Register MCBSPLP_DRR_REG
McBSP Functional Description
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Data Transfer Process for 8- / 12- / 16- / 20- / 24- / 32-bits Long Words
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:
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:
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:
McBSP Basic Programming Model
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:
McBSP Register Manual
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McBSP Register Mapping Summary
:
3160
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
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