Texas Instruments OMAP36 Series, Technical Reference Manual

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McBSP Basic Programming Model
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The mcbsp_clkr and mcbsp_fsr pins can be individually configured as either input or output pins with the
CLKRM and FSRM bits, respectively. The mcbsp_dr pin can only be an input pin.
Table 21-34 shows,
which bits in McBSPi. MCBSPLP_PCR_REG are used to read from/write to these pins.
For the transmitter pins mcbsp_clkx, mcbsp_fsx, and mcbsp_dx, you must meet two conditions:
1. The transmitter of the serial port is in reset (McBSPi. MCBSPLP_SPCR2_REG [0] XRST=0).
2. General–purpose I/O is enabled for the serial port transmitter (McBSPi. MCBSPLP_PCR_REG [12]
XIOEN=1).
The mcbsp_clkx and mcbsp_fsx pins can be individually configured as input or output pins with the
CLKXM and FSXM bits, respectively. The mcbsp_dx pin can only be an output pin.
Table 21-34 shows the
bits in McBSPi. MCBSPLP_PCR_REG used to read from/write to these pins.
For the mcbsp_clks pin (common to all McBSP modules), all of the reset and I/O enable conditions must
be met:
1. Both the receiver and transmitter of the serial port are in reset (RRST=0 and XRST=0).
2. General–purpose I/O is enabled for both the receiver and the transmitter (RIOEN=1 and XIOEN=1).
The mcbsp_clks pin can only be an input pin. To read the status of the signal on the mcbsp_clks pin, read
the McBSPi.
MCBSPLP_PCR_REG [6] CLKS_STAT bit.
Table 21-34. Using McBSP Pins for General-Purpose I/O
Pin General–Purpose Selected as output Output value Selected as input Input value read
use enabled by this when driven from this bit when from this bit
bit combination
XRST = 0
mcbsp_clkx CLKXM = 1 CLKXP CLKXM = 0 CLKXP
XIOEN = 1
XRST = 0
mcbsp_fsx FSXM = 1 FSXP FSXM = 0 FSXP
XIOEN = 1
XRST = 0
mcbsp_dx Always DX_STAT Never Does not apply
XIOEN = 1
RRST = 0
mcbsp_clkr CLKRM = 1 CLKRP CLKRM = 0 CLKRP
RIOEN = 1
RRST = 0
mcbsp_fsr FSRM = 1 FSRP FSRM = 0 FSRP
RIOEN = 1
RRST = 0
mcbsp_dr Never Does not apply Always DR_STAT
RIOEN = 1
RRST = XRST = 0
mcbsp_clks Never Does not apply Always CLKS_STAT
RIOEN = XIOEN = 1
21.5.1.8 Data Packing Examples
This section describes two ways to implement data packing in the McBSP: Using frame length and word
length, and using word length and ignoring frame sync pulses.
21.5.1.8.1 Data Packing Using Frame Length and Word Length
Frame length and word length can be manipulated to pack data effectively. For example, four 8-bit words
are transferred in a single-phase frame, as shown in
Figure 21-70 . In this case:
• (R/X)PHASE = 0: Single-phase frame
• (R/X)FRLEN1 = 00011b: 4-word frame
• (R/X)WDLEN1 = 101b: 32-bit words
Four 8-bit data words are transferred to and from the McBSP by the MPU/IVA2.2 subsystems or the
sDMA controller. Thus, four reads from McBSPi.
MCBSPLP_DRR_REG and four writes to
McBSPi. MCBSPLP_DXR_REG are necessary for each frame.
3150 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated