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McBSP Basic Programming Model
•
RFSREN is equivalent with RINTM = 0b10 setting
•
RSYNCERREN is equivalent with RINTM = 0b11 setting
This interrupt line has its own status register, McBSPi.
21.5.1.4.2.2 Set the transmit interrupt line (legacy only)
The McBSPi.
[5:4] XINTM bit field determines which event generates a transmit
interrupt request (McBSPi_IRQ_TX) to the MPU/IVA2.2 subsystem.
The transmit interrupt informs the MPU/IVA2.2 subsystem of changes to the serial port status. Four
options exist for configuring this interrupt.
•
XINTM = 0b00: The transmit interrupt generated when the McBSPi.
[1] XRDY
bit changes from 0 to 1. Interrupt on every serial word by tracking the XRDY bit. Regardless of the
value of XINTM, XRDY bit can be read to detect the XRDY=1 condition.
•
XINTM = 0b01: The transmit interrupt generated by an end-of-frame condition in the transmit
multichannel selection mode. In any other serial transfer case, this setting is not applicable and,
therefore, no interrupts are generated.
•
XINTM = 0b10: The transmit interrupt generated by a new transmit frame-synchronization pulse.
Interrupt on detection of transmit frame-synchronization pulses. This generates an interrupt even when
the transmitter is in its reset state. This is done by synchronizing the incoming frame-synchronization
pulse to the McBSPi_ICLK clock and sending it to the MPU/IVA2.2 subsystem via transmit interrupt.
•
XINTM = 0b11: The transmit interrupt generated when McBSPi.
[3]
XSYNCERR is set. Interrupt on frame-synchronization error. Regardless of the value of XINTM,
XSYNCERR bit can be read to detect this condition. For information on using XSYNCERR bit, see
.
The McBSP module provides also a common interrupt line McBSPi_IRQ, which can be used by setting the
McBSPi.MCBSPLP_IRQENABLE register. All the above settings have equivalent enable bits in the
McBSPi.MCBSPLP_IRQENABLE register to enable the common interrupt line:
•
XDYEN is equivalent with XINTM = 0b00 setting
•
XEOFEN is equivalent with XINTM = 0b01setting (the interrupt is generated by an end-of-frame
condition regardless of the multichannel selection mode)
•
XFSXEN is equivalent with XINTM = 0b10 setting
•
XSYNCERREN is equivalent with XINTM = 0b11 setting
This interrupt line has its own status register, McBSPi.
21.5.1.5 Receiver Configuration
To configure the McBSP receiver, perform the following procedure:
1. Place the McBSP receiver in reset .
2. Program the McBSP registers for the desired receiver operation.
3. Take the receiver out of reset.
These 3 steps are detailed in the following subsections.
21.5.1.5.1 Resetting (Step 1) and Enabling (Step 3) the Receiver
The first step of the receiver configuration procedure is to reset the receiver, and the last step is to enable
the receiver (to take it out of reset).
The serial port can be reset in the following 2 ways:
1. A global reset places the receiver, transmitter, and SRG in reset. When the device reset is removed,
[6] GRST, McBSPi.
[7] FRST,
[0] XRST bits = 0,
which keeps the entire serial port in the reset state.
3133
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated
