Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 3100 / 3738

Phase 1
(one word of 16 bits)
Phase 2
(one word of 8 bits)
CLK(R/X)
FS(R/X)
D(R/X)
mcbsp-029
DRR_REG
Receive shift
register
(RSR)
Receive buffer
(RB)
mcbspi_dr
To MPU/IVA2 ss
or sDMA
Justify
and bit fill
mcbsp-030
CLKR
DR
FSR
A1
B7 B6
B5 B4 B3 B2 B1
B0
A0
C7 C6 C5
RRDY
RB to DRR copy (A)
Read from DRR (A)
RB to DRR copy (B)
Read from DRR (B)
RRDY: Status of receiver ready bit (high is 1)
mcbsp-031
Public Version
McBSP Functional Description
www.ti.com
Figure 21-30. Dual-Phase Frame for a McBSP Data Transfer
21.4.2.5 McBSP Reception
This section explains the fundamental process of reception in the McBSP module. For details about how
to program the McBSP receiver, see
Section 21.5 , Section 21.5.1.4 , and Section 21.5.1.5 .
Figure 21-31 and Figure 21-32 below show how reception occurs in the McBSP module. A description of
the process follows the figures. Figure 21-31 shows the physical path for the data.
Figure 21-31. McBSP Reception Physical Data Path
Figure 21-32 is a timing diagram showing signal activity for one possible reception scenario.
Figure 21-32. McBSP Reception Signal Activity
The following process describes how data travels from the mcbspi_dr pin to the MPU/IVA2.2 subsystem or
to the sDMA controller:
1. The McBSP module waits for a receive frame-synchronization pulse on FSR_int.
2. When the pulse arrives, the McBSP module inserts the appropriate data delay that is selected with the
McBSPi. MCBSPLP_RCR2_REG [1:0] RDATDLY bits. In the preceding timing diagram a 1-bit data
delay is selected.
3. The McBSP module accepts data bits on the mcbspi_dr pin and shifts them into the RSR. For details
on choosing a word length, see Section 21.5.1.5.2.2.2 .
4. When a full word is received, the McBSP module copies the contents of the RSR to the RB, provided
that RB is not full.
5. When the programmed receive threshold is reached (McBSPi. MCBSPLP_THRSH1_REG [10:0]
RTHRESHOLD field), the McBSP module asserts the receiver ready bit
(McBSPi.
MCBSPLP_SPCR1_REG [1] RRDY bit). This indicates that receive data is ready to be read
by the MPU/IVA2.2 subsystem or the sDMA controller by accessing McBSPi. MCBSPLP_DRR_REG
register.
The data copied from RB to McBSPi.
MCBSPLP_DRR_REG is justified and bit filled according to the
McBSPi. MCBSPLP_SPCR1_REG [14:13] RJUST field.
3100 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated