Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 3131 / 3738

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McBSP Basic Programming Model
Table 21-25. Input Clock Selection for Sample Rate Generator
SCLKME bit CLKSM bit Input Clock for Sample Rate Generator
0 0 Signal on mcbsp_clks pin
0 1 McBSPi_ICLK clock
1 0 Signal on mcbsp_clkr pin
1 1 Signal on mcbsp_clkx pin
21.5.1.3 Data Transfer DMA Request Configuration
To configure the McBSP receive/transmit data DMA requests (McBSPi_DMA_RX and McBSPi_DMA_TX),
perform the following procedure:
• Write the receive McBSPi. MCBSPLP_THRSH1_REG register with the required receive DMA request
length (the length of the transfer is the same as the threshold value + 1). As long as the RB occupied
locations level is above or equal to the THRSH1_REG value + 1, the DMA request will be asserted.
After transferring the configured THRSH1_REG value + 1 number of words, the receive DMA request
will be de-asserted and reasserted as soon as the conditions are met again.
NOTE: In case of a number of transfers that exceed the number of the programmed DMA length
the McBSP module will respond to the command, and will perform the transfer regardless of
the receive buffer empty condition. When the receive buffer is empty a data transfer access
will trigger a receive underflow interrupt, if enabled by
McBSPi.
MCBSPLP_IRQENABLE_REG [4] RUNDFLEN bit.
• Write the transmit McBSPi. MCBSPLP_THRSH2_REG register with the required transmit DMA request
length (the length of the transfer is the same as the threshold value + 1). As long as the XB free
locations level is above or equal to the THRSH2_REG value + 1, the DMA request will be asserted.
After transferring the configured THRSH2_REG value + 1 number of words, the transmit DMA request
will be de-asserted and reasserted as soon as the conditions are met again.
NOTE: In case of a number of transfers that exceed the number of the programmed DMA length
the McBSP module will respond to the command, and will perform the transfer regardless of
the transmit buffer full condition. When the transmit buffer is full a data transfer access will
trigger a transmit overflow interrupt, if enabled by McBSPi.
MCBSPLP_IRQENABLE_REG [12]
XOVFLEN bit.
21.5.1.4 Interrupt Configuration
The McBSP module offers two interrupt schemes:
• L4 compliant interrupt request scheme using a common receive/transmit interrupt request line
• The legacy interrupt compliant scheme using 3 interrupt lines: one for receive, one for transmit and the
common interrupt line.
21.5.1.4.1 L4-Compliant Interrupt Line
The L4-compliant interrupt line can be configured by using the McBSPi. MCBSPLP_IRQENABLE_REG
register. When the McBSPi. MCBSPLP_IRQSTATUS_REG bit is set and the corresponding
McBSPi. MCBSPLP_IRQENABLE_REG bit is set to one, the interrupt line is asserted. Writing one to a bit
in McBSPi. MCBSPLP_IRQSTATUS_REG register clears the bit.
There are several conditions, which can be configured to generate an interrupt as follows:
1. Transmit buffer empty at end of frame (McBSPi. MCBSPLP_IRQSTATUS_REG [14] XEMPTYEOF bit is
set to one when a complete frame was transmitted and the transmit buffer is empty .
2. Transmit buffer overflow (McBSPi. MCBSPLP_IRQSTATUS_REG [12] XOVFLSTAT bit is set to one
when transmit buffer overflow; the data written while overflow condition is discarded).
3. Transmit buffer underflow (McBSPi. MCBSPLP_IRQSTATUS_REG [11] XUNDFLSTAT bit is set to one
when the transmit data buffer is empty, new data needs to be transmitted).
3131 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
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