Texas Instruments OMAP36 Series, Technical Reference Manual

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McBSP Register Manual
Bits Field Name Description Type Reset
31:16 RESERVED Read returns 0x0. R 0x0000
15:0 FIRCOEFF FIR coefficients control register (the coefficients are RW 0x0000
programmed by successive write sequence of all 128 FIR
coefficients)
The write sequence should start with the coefficient 0.
In order to enable the write to this register the
COEFFWREN bit in SSELCR_REG should be set to one.
When this bit is set the read operation will return only the
last written value.
After a complete FIR coefficients write sequence the
COEFFWREN should be set to zero.
A read sequence from SFIRCR_REG while
COEFFWREN is set to zero will return the coefficients
values starting from 0 to 127.
The write coefficient address is set to 0 by the change of
COEFFWREN from 0 to 1.
The read coefficient address is set to 0 by the change of
COEFFWREN from 1 to 0
Table 21-145. Register Call Summary for Register ST_SFIRCR_REG
McBSP Basic Programming Model
• SIDETONE Initialization Procedure : [0] [1]
• SIDETONE FIR Coefficients Writing : [2]
• SIDETONE FIR Coefficients Reading : [3]
McBSP Register Manual
• SIDETONE Register Mapping Summary : [4] [5]
Table 21-146. ST_SSELCR_REG
Address Offset 0x0000 002C
Physical Address 0x4902 802C Instance SIDETONE_McBSP2
0x4902 A02C SIDETONE_McBSP3
Description Sidetone select register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
COEFFWREN SIDETONEEN
COEFFWRDONE
Bits Field Name Description Type Reset
31:3 RESERVED Read returns 0x0. R 0x00000000
2 COEFFWRDONE Write FIR coefficients completed. R 0x0
0x0: FIR coefficients not loaded
0x1: FIR coefficients loaded
3207 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
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