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McBSP Basic Programming Model
below).
•
Select the input/output channels configured as SIDETONE channels by setting the following bit fields
listed in
Table 21-35. Selection of the SIDETONE Input and Output Channels
Bit field
Description
McBSPi.
[9:7]
Map the CH1 data for the speaker out channels to one of the McBSP channels
OCH1ASSIGN
(1 out of 8 channels)
McBSPi.
[6:4]
Map the CH0 data for the speaker out channels to one of the McBSP channels
OCH0ASSIGN
(1 out of 8 channels)
McBSPi.
[3:2]
Map the CH1 data from the digital microphone channels to one of the McBSP
ICH1ASSIGN
channels (1 out of 4 channels)
McBSPi.
[1:0]
Map the CH0 data from the digital microphone channels to one of the McBSP
ICH0ASSIGN
channels (1 out of 4 channels)
•
Enable SIDETONE by setting 2 bits to 1:
1. In McBSP module, the McBSPi.
[10] SIDETONEEN bit
2. In SIDETONE core, the McBSPi.
[0] SIDETONEEN bit
NOTE:
Word width in the loop is 24 bits. If input channel word width is less than 24 bits, LSBs of
the samples are zero padded. If input channel word width is more than 24 bits, samples are
truncated.
21.5.2.2 SIDETONE Initialization Procedure
The SIDETONE core initialization procedure is as follows:
1. Write 1 in McBSPi.
[1] COEFFWREN bit to enable loading of the FIR coefficients.
2. Load one by one the FIR coefficients performing 128 write accesses to
[15:0] FIRCOEFF bit field, the McBSPi.
[0] FIRCOEFF bit
is loaded first. To ensure the completion of loading, check the status bit-field,
McBSPi.
[2] COEFFWRDONE bit.
3. Set-up gain values for both channels writing desired values inside McBSPi.
[31:16]
CH1GAIN bit field for the second sidetone channel and McBSPi.
[15:0] CH0GAIN
bit field for the first sidetone channel.
21.5.2.3 SIDETONE FIR Coefficients Writing
Writing the coefficients is only possible when the SIDETONE is disabled.
1. Write 1 in McBSPi.
[1] COEFFWREN bit to enable writing of the FIR coefficients, or
write 0, and then write 1 in the COEFFWREN bit to reset the write process.
2. Perform 128 write accesses in 32/16 LSB bit mode on the McBSPi.
FIRCOEFF bit field. The first write action following the previous step sets the coefficient index 0.
3. Check that the write is done by reading McBSPi.
[2] COEFFWRDONE bit (it
becomes 1 after the 128th coefficient is written).
21.5.2.4 SIDETONE FIR Coefficients Reading
Reading the coefficients is only possible when the SIDETONE is disabled.
•
Write 0 in McBSPi.
[1] COEFFWREN bit to enable reading of the FIR coefficients, or
write 1, and then write 0 in the COEFFWREN bit to reset the read process.
•
Perform 128 read accesses from McBSPi.
[15:0] FIRCOEFF bit field. Each read
returns coefficients one by one. The first read following previous step returns coefficient index 0.
3153
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated
