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MMC/SD/SDIO Register Manual
Bits
Field Name
Description
Type
Reset
0
MCKD
MMC clock output signal data value.
RW
0
Read 0x0:
No action. Returns 0.
Write 0x0:
The output clock is driven low.
Read 0x1:
No action. Returns 1.
Write 0x1:
The output clock is driven high.
Table 24-42. Register Call Summary for Register MMCHS_SYSTEST
MMC/SD/SDIO Register Manual
•
•
:
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26]
[27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54]
[55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72]
Table 24-43. MMCHS_CON
Address Offset
0x02C
Physical Address
0x4809 C02C
Instance
MMCHS1
0x480A D02C
MMCHS3
0x480B 402C
MMCHS2
Description
Configuration register
This register is used:
- to select the functional mode for any card.
- to send an initialization sequence to any card.
- to enable the detection on the mmci_dat[1] signal of a card interrupt for SDIO cards only.
And also to configure:
- specific data and command transfers for MMC cards only.
- the parameters related to the card detect and write protect input signals.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
DVAL
HR
OD
MIT
INIT
STR
CDP
DW8
WPP
OBIE
OBIP
CTPL
MODE
CEATA
PADEN
CLKEXTFREE
Bits
Field Name
Description
Type
Reset
31:17
Reserved
Reserved bit field. Do not write any value
R
0x00000
16
CLKEXTFREE
External clock free running.
RW
0
This register is used to maintain card clock out of transfer
transaction to enable slave module (for example to generate a
synchronous interrupt on mmci_dat[1]). The Clock will be maintain
only if MMCi.
[2] CEN bit is set.
0x0:
External card clock is cut off outside active transaction
period.
0x1:
External card clock is maintain even out of active
transaction period only if MMCi.
CEN bit is set.
15
PADEN
Control Power for MMC Lines.
RW
0
This register is only useful when MMC PADs contain power saving
mechanism to minimize its leakage power. It works as a GPIO that
directly control the ACTIVE pin of PADs. Excepted for
mmci_dat[1], the signal is also combine outside the module with
the dedicated power control MMCi.
[11] CTPL bit.
0x0:
ADPIDLE module pin is not forced, it is automatically
generated by the MMC fsms.
0x1:
ADPIDLE module pin is forced to active state.
3431
SWPU177N – December 2009 – Revised November 2010
MMC/SD/SDIO Card Interface
Copyright © 2009–2010, Texas Instruments Incorporated
