Texas Instruments OMAP36 Series, Technical Reference Manual

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A1
Internal
CLK(R/X)
D(R/X)
Internal
FS(R/X)
A0
B7 B6
B5 B4 B3 B2 B1
B0
mcbsp-026
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McBSP Functional Description
Table 21-15. Receiver Clock Mode
Value Digital loop back mode mcbspi_clkr pin Description
0x0 McBSPi. MCBSPLP_XCCR_REG [5] DLB bit input CLKR_int is driven by an external clock
=0
McBSPi. MCBSPLP_XCCR_REG [5] DLB bit High-impedance CLKR_int is driven by CLKX_int. The CLKX_int is
=1 derived based on the CLKXM value.
0x1 McBSPi. MCBSPLP_XCCR_REG [5] DLB bit output CLKR_int is driven by the internal sample rate
=0 generator
McBSPi. MCBSPLP_XCCR_REG [5] DLB bit output CLKR_int is driven by CLKX_int. The CLKX_int is
=1 derived based on the CLKXM value.
The polarities of CLKR and CLKX signals are configured in McBSPi. MCBSPLP_PCR_REG register.
The McBSPi. MCBSPLP_PCR_REG [1] CLKXP defines the transmit clock polarity:
• When set to 0, transmit data driven on rising edge of CLKX signal
• When set to 1, transmit data driven on falling edge of CLKX signal
The McBSPi. MCBSPLP_PCR_REG [0] CLKRP defines the receive clock polarity:
• When set to 0, receive data sampled on falling edge of CLKX signal
• When set to 1, transmit data sampled on rising edge of CLKX signal
Figure 21-27 gives an example where the clock signal controls the timing of each bit transfer on the pin.
Figure 21-27. Clock Signal Control of Bit Transfer Timing
NOTE: The McBSP module is constrained to operate at an internal functional frequency of up to L4
interface frequency divided by 2. When driving CLKX or CLKR at the pin, choose an
appropriate input clock frequency. When using the internal sample rate generator for
CLKX/CLKR/CLKS, choose an appropriate input clock frequency (up to L4 interface
frequency) and divide down value by programming the
McBSPi.
MCBSPLP_SRGR1_REG [7:0] CLKGDV bit field.
21.4.2.3.2 Serial Words
Bits traveling between a shift register (RSR or XSR) and a data pin (mcbspi_dr or mcbspi_dx) are
transferred in a group called a serial word. The software defines how many bits are in a word by
programming:
• For the receiver: the McBSPi. MCBSPLP_RCR1_REG [7:5] RWDLEN1 field and the
McBSPi. MCBSPLP_RCR2_REG [7:5] RWDLEN2 field.
• For the transmitter: the McBSPi. MCBSPLP_XCR1_REG [7:5] XWDLEN1 field and the
McBSPi. MCBSPLP_XCR2_REG [7:5] XWDLEN2 field.
The difference of use is explained to Section 21.4.2.4.1 .
The various possibilities of word length are 8, 12, 16, 20, 24, and 32 bits (for field values, see
Section 21.6 )
Bits coming from the mcbspi_dr pin are held in the RSR until it holds a full serial word, then the word is
passed to the RB and to the McBSPi.
MCBSPLP_DRR_REG register.
3095 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated