Texas Instruments OMAP36 Series, Technical Reference Manual

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SCM Functional Description
– CONTROL. CONTROL_PROT_ERR_STATUS_DEBUG [02] = GPMC protection violation
– CONTROL. CONTROL_PROT_ERR_STATUS_DEBUG [03] = SMS protection violation
– CONTROL. CONTROL_PROT_ERR_STATUS_DEBUG [06] = IVA2.2 protection violation
– CONTROL. CONTROL_PROT_ERR_STATUS_DEBUG [12] = L3 RT protection violation
For more information, see Chapter 9 , Interconnect.
13.4.9 SDRC Registers
Table 13-28 lists the SDRAM controller (SDRC) registers, which export reset values to the SDRC
registers.
Table 13-28. SDRC Registers
Physical Address Register Name Description Access
0x4800 2460 CONTROL_SDRC_SHARING SDRC sharing configuration R/W
0x4800 2464 CONTROL_SDRC_MCFG0 SDRC configuration register 0 R/W
0x4800 2468 CONTROL_SDRC_MCFG1 SDRC configuration register 1 R/W
At reset, the following occur:
•
CONTROL. CONTROL_SDRC_SHARING [30:0] copies into SDRC.SDRC_SHARING[30:0].
• CONTROL. CONTROL_SDRC_MCFG0 [30:0] copies into SDRC.SDRC_MCFG_0[30:0].
• CONTROL. CONTROL_SDRC_MCFG1 [30:0] copies into SDRC.SDRC_MCFG_1[30:0].
When LOCK bit SDRC.SDRC_SHARING[30] is set, a copy of SDRC.SDRC_SHARING[30:0] is made into
CONTROL.
CONTROL_SDRC_SHARING [30:0].
When LOCK bit SDRC.SDRC_MCFG_0[30] is set, a copy of SDRC.SDRC_MCFG_0[30:0] is made into
CONTROL.
CONTROL_SDRC_MCFG0 [30:0].
When LOCK bit SDRC.SDRC_MCFG_1[30] is set, a copy of SDRC.SDRC_MCFG_1[30:0] is made into
CONTROL.
CONTROL_SDRC_MCFG1 [30:0].
13.4.10 Debug and Observability
13.4.10.1 Description
Figure 13-17 is an overview of observability multiplexing, which minimizes the number of signals
exchanged at the power domain boundary.
2485 SWPU177N – December 2009 – Revised November 2010 System Control Module
Copyright © 2009–2010, Texas Instruments Incorporated