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HDQ/1-Wire Basic Programming Model
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18.5 HDQ/1-Wire Basic Programming Model
The HDQ/1-Wire module can be considered a simple byte engine because it only implements the
hardware interface layer for both HDQ and 1-Wire protocols. The correct sequencing is controlled by the
firmware, which is described in this section.
18.5.1 Module Initialization Sequence
18.5.1.1 Mode Selection
MODE bit HDQ.
[0] allows selection between the HDQ and 1-Wire protocols. When
set to 0, the protocol is HDQ; when set to 1, the protocol is 1-Wire. The bit is assumed static for design
purposes. The configuration is in HDQ mode by default.
Although this bit can be modified at any point, it is strongly recommended that it be modified only as part
of the boot-up configuration.
18.5.1.2 Reset/Initialization
No slave presence test is required in HDQ mode; however, the slave can be reset by setting the
INITIALIZATION bit HDQ.
[4]. The line
is then pulled down (break pulse) and the bit returns to 0 after the pulse is sent. Upon completion, a
time-out interrupt is also generated. The slave does not respond to this pulse.
In 1-Wire mode, the slave returns a presence pulse when it receives the initialization pulse. The protocol
for initialization is as follows:
1. Set the INITIALIZATION bit HDQ.
[2] to 1 and the GO bit
HDQ.
[4] to 1 to send the pulse. When the pulse is sent, the bit is cleared in the
register.
2. Wait for the presence detect flag (TIMEOUT bit HDQ.
[0]) to generate an interrupt.
This flag is set when the response time allowed to the slave has elapsed, whether it has sent a pulse
or not.
3. Read the HDQ.
register to check whether the presence pulse has been received
before starting any transfer.
18.5.2 HDQ Protocol Basic Programming Model
18.5.2.1 Write Operation
The write operation sequence is as follows:
1. Write the command/address or data value to the TX write register (HDQ.
).
NOTE:
Steps 2 and 3 can be performed simultaneously.
2. Set DIR bit HDQ.
[1] to indicate a write.
3. Set GO bit HDQ.
[4] to start the transmission.
(a) The hardware sends the byte from the TX write register.
(b) In a write operation, the TIMEOUT bit is always cleared, because there is no acknowledge
mechanism from the slave.
(c) When the write operation is completed, the TX-complete flag is set in the interrupt status register
(TXCOMPLETE bit HDQ.
[2]). If interrupts are masked (that is, the
corresponding bit has been previously set in the control and status register), no interrupt signal is
generated.
(d) The GO bit HDQ.
[4] is cleared at the end of a write operation.
4. The software must read the interrupt status register to clear the interrupt.
5. Repeat step 1 through step 4 for each successive byte to write.
2854
HDQ/1-Wire
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
