Texas Instruments OMAP36 Series, Technical Reference Manual

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HDQ/1-Wire Register Manual
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TIMEOUT
TXCOMPLETE
RXCOMPLETE
Bits Field Name Description Type Reset
31:3 Reserved Reads return 0s. R 0x00000000
2 TXCOMPLETE TX-complete interrupt flag R 0
Set to 1 if cause of interrupt.
Set to 0 when register read.
1 RXCOMPLETE Read-complete interrupt flag R 0
Set to 1 if cause of interrupt.
Set to 0 when register read.
0 TIMEOUT Presence detect/timeout interrupt flag R 0
In 1-Wire mode, set to 1 if slave's presence detected.
In HDQ mode, set to 1 if timeout on read occurs.
Set to 0 when register read.
Table 18-17. Register Call Summary for Register HDQ_INT_STATUS
HDQ/1-Wire Functional Description
• Description : [0] [1] [2]
• Interrupt Conditions : [3] [4] [5]
• Description : [6] [7]
• Interrupt Conditions : [8] [9] [10]
• Status Flags : [11]
HDQ/1-Wire Basic Programming Model
• Reset/Initialization : [12]
• Write Operation : [13]
• Read Operation : [14] [15]
• Write Operation : [16] [17]
• Read Operation : [18] [19]
• 1-Wire Bit Mode Operation : [20] [21]
• Module Power-Down Mode : [22] [23] [24]
• System Idle Mode : [25] [26] [27] [28]
HDQ/1-Wire Register Manual
• HDQ/1-Wire Register Mapping Summary : [29]
Table 18-18. HDQ_SYSCONFIG
Address Offset 0x014
Physical Address 0x480B 2014 Instance HDQ/1-Wire
Description This register controls various bits.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
AUTOIDLE
SOFTRESET
2865 SWPU177N – December 2009 – Revised November 2010 HDQ/1-Wire
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