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HDQ/1-Wire Register Manual
18.7 HDQ/1-Wire Register Manual
18.7.1 HDQ/1-Wire Instance Summary
lists the HDQ/1-Wire instances.
Table 18-6. Instance Summary
Module Name
Base Address
Size
HDQ/1-Wire
0x480B 2000
4K bytes
CAUTION
All reserved bits must be written with 0. There is no synchronization between
the register clock domain and the state-machine domain. Therefore, the
following rules must be observed when accessing the module registers:
•
A read from the interrupt status register or the receive buffer register is not
allowed unless the processor has been interrupted by the module.
•
After the release of the GO bit in the control and status register, no access
to the TX data register or the control and status register is allowed until the
processor has been interrupted by the module.
•
Polling of the interrupt status register by software to determine whether an
interrupt was generated is not allowed.
•
No access to the module registers should be done after the software puts
the module in power-down mode (by setting bit 5 of the control and status
register to 0) except to re-enable the clock.
CAUTION
The HDQ/1-Wire registers are limited to 32-bit data accesses. 16-bit and 8-bit
are not allowed and can corrupt register content.
18.7.2 HDQ/1-Wire Register Mapping Summary
lists the HDQ/1-Wire registers.
Table 18-7. HDQ/1-Wire Register Summary
Register Name
Type
Register Width (Bits)
Address Offset
HDQ/1-Wire Physical
Address
R
32
0x000
0x480B2000
RW
32
0x004
0x480B2004
R
32
0x008
0x480B2008
RW
32
0x00C
0x480B200C
R
32
0x010
0x480B2010
RW
32
0x014
0x480B2014
R
32
0x018
0x480B2018
2861
SWPU177N – December 2009 – Revised November 2010
HDQ/1-Wire
Copyright © 2009–2010, Texas Instruments Incorporated
