Public Version
HDQ/1-Wire Register Manual
www.ti.com
Bits
Field Name
Description
Type
Reset
0x1:
Enable clocks
4
GO
Go bit
RW
0
Write 1 to send the appropriate commands.
Bit returns to 0 after the command is complete.
3
PRESENCEDETECT
Presence detect received, 1-Wire mode only
R
0
0x0:
Not detected
0x1:
Detected
2
INITIALIZATION
Write 1 to send initialization pulse.
RW
0
Bit returns to 0 after pulse is sent.
1
DIR
DIR bit, determines if next command is read or write
RW
0
0x0:
Write
0x1:
Read
0
MODE
Mode selection bit
RW
0
0x0:
HDQ mode
0x1:
1-Wire mode
Table 18-15. Register Call Summary for Register HDQ_CTRL_STATUS
HDQ/1-Wire Environment
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HDQ Protocol Initialization (Default)
HDQ/1-Wire Functional Description
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:
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1-Wire Single-Bit Mode Operation
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:
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HDQ/1-Wire Basic Programming Model
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:
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:
[18] [19] [20] [21] [22] [23] [24]
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:
[27] [28] [29] [30] [31] [32] [33]
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:
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HDQ/1-Wire Use Cases and Tips
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Pad Configuration and HDQ/1-Wire clock and power management
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:
HDQ/1-Wire Register Manual
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HDQ/1-Wire Register Mapping Summary
Table 18-16. HDQ_INT_STATUS
Address Offset
0x010
Physical Address
0x480B 2010
Instance
HDQ/1-Wire
Description
This register controls interrupt status.
Type
R
2864
HDQ/1-Wire
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated