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HDQ/1-Wire Functional Description
18.4.3 1-Wire Mode
18.4.3.1 1-Wire Mode Features
The 1-Wire mode supports the following:
•
Dallas Semiconductor 1-Wire protocol
•
Power-down mode
•
Single-bit mode
18.4.3.2 Description
The 1-Wire mode requires an initialization pulse to be sent to the slave(s) connected on the interface. If a
slave is present, it responds with a presence pulse.
The initialization pulse is sent after INITIALIZATION bit HDQ.
[2] is set. The firmware
sends the initialization pulse depending on the value of this bit.
The slave presence on the line is detected by a presence bit in the control and status register. When the
slave receives the initialization pulse, it sends back its presence pulse by pulling down the line. The
module detects this low-going edge and sets the PRESENCEDETECT bit HDQ.
[3].
In a similar way, if a presence pulse is not received from the slave after an initialization pulse is sent, the
PRESENCEDETECT bit remains cleared.
Whether or not a presence pulse is detected after an initialization pulse is sent, the TIMEOUT bit
HDQ.
[0] is set and an interrupt condition is generated.
In 1-Wire mode, the generated interrupt condition means the maximum time allowed for receiving the
response has elapsed and the software must check the PRESENCEDETECT bit to determine whether or
not there was a presence pulse.
The INITIALIZATION bit is cleared at the end of the initialization pulse at the same time as the TIMEOUT
bit is set. The TIMEOUT bit is cleared when the interrupt status register (HDQ.
) is
read.
For read operations, 1-Wire is a bit-by-bit protocol, which means the slave must be clocked by the host for
each bit of the byte to read.
The line is pulled up at the end of the command/address byte. On the first read, the host creates a
low-going edge to initiate a bit read. The line is then pulled up (pulled to the high-impedance state by the
host and set to a high logical level by the external pullup) and the slave either drives the line low to
transmit a 0 or does not drive the line to transmit a 1. This sequence is repeated for each bit to read.
The first bit the host receives is the LSB, and the last bit is the most significant bit (MSB) in the receive
data register (HDQ.
An interrupt condition indicates either a TX-complete, an RX-complete, or a time-out condition (that is, the
time allowed for the slave to indicate its presence has elapsed). A read operation on the interrupt status
register clears the interrupt conditions previously set. As in the HDQ mode, only one interrupt signal is
sent to the MPU. Only an overall mask bit can enable or disable the interrupt (the interrupt conditions
cannot be masked individually).
18.4.3.3 1-Wire Single-Bit Mode Operation
A single-bit mode can be entered by setting the appropriate bit in the control and status register
(1_WIRE_SINGLE_BIT bit HDQ.
[7]). In this mode, only one bit of data at a time is
transferred between the master and the slave. After the bit is transferred, an interrupt is generated (that is,
there is an RX-complete for a read operation and a TX-complete for a write operation). Bit 0 of the RX
register (HDQ.
) is updated each time a bit is received from the slave; bit 0 of the TX
register (HDQ.
) contains the bit to be sent.
2851
SWPU177N – December 2009 – Revised November 2010
HDQ/1-Wire
Copyright © 2009–2010, Texas Instruments Incorporated
