Texas Instruments OMAP36 Series, Technical Reference Manual

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HDQ/1-Wire Register Manual
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18.7.3 HDQ/1-Wire Register Description
Table 18-8 through Table 18-20 describe the individual bits of the HDQ/1-Wire registers.
Table 18-8. HDQ_REVISION
Address Offset 0x000
Physical Address 0x480B 2000 Instance HDQ/1-Wire
Description This register contains the IP revision code.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved REVISION
Bits Field Name Description Type Reset
31:8 Reserved Reads return 0s. R 0x000000
7:0 REVISION IP revision R See
(1)
.
The 4 LSBs indicate a minor revision.
The 4 MSBs indicate a major revision.
Ex: 0x21: Revision 2.1
(1)
TI internal data
Table 18-9. Register Call Summary for Register HDQ_REVISION
HDQ/1-Wire Register Manual
• HDQ/1-Wire Register Mapping Summary : [0]
Table 18-10. HDQ_TX_DATA
Address Offset 0x004
Physical Address 0x480B 2004 Instance HDQ/1-Wire
Description This register contains the data to be transmitted.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved TX_DATA
Bits Field Name Description Type Reset
31:8 Reserved Reads return 0s. R 0x000000
7:0 TX_DATA Transmit data (used in both HDQ and 1-Wire modes) RW 0x00
Table 18-11. Register Call Summary for Register HDQ_TX_DATA
HDQ/1-Wire Environment
• HDQ Protocol Initialization (Default) : [0]
HDQ/1-Wire Functional Description
• 1-Wire Single-Bit Mode Operation : [1]
HDQ/1-Wire Basic Programming Model
• Write Operation : [2]
• Read Operation : [3]
• Write Operation : [4]
• Read Operation : [5] [6]
• 1-Wire Bit Mode Operation : [7]
HDQ/1-Wire Register Manual
• HDQ/1-Wire Register Mapping Summary : [8]
2862HDQ/1-Wire SWPU177N – December 2009 – Revised November 2010
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