Public Version
HDQ/1-Wire Basic Programming Model
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18.5.3.2 Read Operation
The read operation sequence is as follows:
1. Write the address to the TX write register (HDQ.
).
2. Set DIR bit HDQ.
[4] to 1 and
wait for the TX-complete interrupt flag.
3. Write the command value to the TX write register (HDQ.
).
4. Set DIR bit HDQ.
[1] to 0 and GO bit HDQ.
[4] to 1 and wait
for the TX-complete interrupt flag.
NOTE:
Steps 5 and 6 can be performed simultaneously.
5. Set DIR bit HDQ.
[1] to 1 to indicate a read.
6. Set GO bit HDQ.
[4] to 1 to start the transmission.
(a) The hardware (master) generates a low-going edge and clocks 8 bits of data into the RX receive
register (HDQ.
). The first bit received is the LSB and the last bit is the MSB.
(b) TIMEOUT bit HDQ.
[0] is always cleared in a read operation.
(c) When the operation is complete, the RX-complete flag is set in the interrupt status register
(RXCOMPLETE bit HDQ.
[1]). No interrupt signal is generated if the interrupts
are masked (that is, the corresponding bit was previously set in the control and status register).
(d) GO bit HDQ.
[4] is cleared at the end of the read. It is also cleared if a
time-out occurs.
7. The software must read the interrupt status register to determine whether an RX was successfully
completed or a time-out occurred.
8. The software reads the RX receive buffer register (HDQ.
) to retrieve the read data
from the slave.
9. Repeat step 1 through step 8 for each successive byte.
18.5.3.3 1-Wire Bit Mode Operation
Select the single-bit mode by setting the 1_WIRE_SINGLE_BIT bit HDQ.
[7] to 1. In
this mode, only one bit of data at a time is transferred between the master and the slave. After the bit is
transferred, the corresponding interrupt flag is set (that is, there is an RX-complete (RXCOMPLETE bit
HDQ.
[1]) for a read operation and a TX-complete (TXCOMPLETE bit
HDQ.
[2]) for a write operation). Bit 0 of the RX register (HDQ.
) is
updated each time a bit is received; bit 0 of the TX register (HDQ.
) contains the bit of data
to be sent.
18.5.4 Power Management
The software has independent control of the two clock domains (interconnect clock: HDQ_ICLK and
functional clock: HDQ_FCLK). Because there is no acknowledge mechanism from the HDQ/1-Wire
module to an idle request, the software must ensure that a clock is not shut off while a transfer is being
processed (the data would be lost).
If the autoidle function (AUTOIDLE bit HDQ.
[0] set to 1) provides a safe transfer (the
module wakes up the HDQ_ICLK as soon as a transfer is initiated), the power-down mode and the PRCM
idle requests (through the whole L4 clock domain idle request) must be handled carefully.
The following sections describe the steps to follow to use the power-down and idle modes.
18.5.4.1 Module Power-Down Mode
1. Before shutting off the HDQ_FCLK, wait for an RX-complete or a TX-complete interrupt.
•
In a read operation, the transfer is completed when the RX-complete flag (RXCOMPLETE bit
HDQ.
[1]) generates an interrupt.
•
In a write operation, the transfer is completed when the TX-complete flag (TXCOMPLETE bit
HDQ.
[2]) generates an interrupt. The software must check whether the
interrupt was generated after the address/command byte was sent or after the data byte was sent.
2856
HDQ/1-Wire
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
