Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2852 / 3738

Public Version
HDQ/1-Wire Functional Description
www.ti.com
18.4.3.4 Interrupt Conditions
The HDQ/1-Wire module provides the following interrupt status:
1. Transmission complete:
A write operation of one byte was completed. Successful or failed completion is not indicated, because
there is no acknowledgment from the slave in 1-Wire protocol. This interrupt condition is cleared by
reading the interrupt status register (HDQ.
HDQ_INT_STATUS ).
2. Read complete:
In 1-Wire mode, the interrupt status indicates that a byte has been successfully read. This interrupt
condition is cleared by reading the interrupt status register (HDQ.
HDQ_INT_STATUS ).
3. Presence detect/time-out:
In 1-Wire mode, the interrupt status indicates that it is now valid to check the PRESENCEDETECT bit.
This interrupt condition is cleared by reading the interrupt status register (HDQ.
HDQ_INT_STATUS ).
Only one interrupt is generated to the MPU based on any of these interrupt conditions. A read operation
on the interrupt status register clears all interrupt status bits that were previously set.
18.4.3.5 Status Flags
The presence-condition-detected status flag is contained in the PRESENCEDETECT bit
HDQ.
HDQ_CTRL_STATUS [3]. This is valid only in 1-Wire mode. The flag is updated when TIMEOUT bit
HDQ. HDQ_INT_STATUS [0] is set. Therefore, its correct value shows only after the interrupt is generated.
The firmware must wait for the time-out condition; otherwise, the flag keeps its previous value and is
undefined.
18.4.4 Module Power Saving
18.4.4.1 Autoidle Mode
The HDQ/1-Wire module provides an autoidle function in its interconnect clock domain.
The interconnect clock autoidle power-saving mode is enabled or disabled through the AUTOIDLE bit
HDQ.
HDQ_SYSCONFIG [0]. When this mode is enabled and there is no activity on the interconnect
interface, the interconnect clock (HDQ_ICLK) is disabled inside the module, thereby reducing power
consumption. When there is new activity on the interconnect interface, the interconnect clock is restarted
with no latency penalty. This mode is disabled by default after a reset.
This mode is recommended to reduce power consumption.
18.4.4.2 Power-Down Mode
The HDQ/1-Wire module also provides a power-saving function in its functional clock domain.
Setting the CLOCKENABLE bit in the control and status register (CLOCKENABLE bit
HDQ.
HDQ_CTRL_STATUS [5]) to 0 shuts off the functional clock (HDQ_FCLK) to the state-machine. The
state-machine is reset when the functional clock is disabled; if any transaction is ongoing, it is aborted into
the reset state.
The register values are not affected by disabling the functional clock.
Do not access the module registers after the software has put the module in power-down mode except to
write to the CLOCKENABLE bit to take the module out of power-down mode.
18.4.5 System Power Management and Wakeup
As part of the system-wide power-management scheme, the HDQ/1-Wire module can go into idle state at
the request of the PRCM module (for more information, see
Chapter 3 , Power, Reset, and Clock
Management). However, the HDQ/1-Wire module does not support handshake protocol with the PRCM.
The HDQ/1-Wire module can go into idle mode only as part of the L4 interconnect clock domain (both
CORE_L4_ICLK and FUNC_12M_CLK belong to the L4 interconnect clock domain).
2852 HDQ/1-Wire SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated