Device
System control module
CORE power domain
IO_CTRL
WKUP power
domain
hw_dbg0
hw_dbg17
hw_dbgn
CORE_OBSMUX0
CORE_OBSMUXN
CORE_OSBMUS17
O
B
S
M
U
X
0
O
B
S
M
U
X
N
O
B
S
M
U
X
1
7
W
K
U
P
O
B
S
M
U
X
1
7
W
K
U
P
O
B
S
M
U
X
0
0
127
0
31
W
K
U
P
O
B
S
M
U
X
N
Device
modules
scm-017
Core control
module
Wake-up
control
module
Public Version
SCM Functional Description
www.ti.com
Figure 13-17. Overview of the Debug and Observability Register Functionality
Two layers of multiplexer are used to select the set of internal observable signals (PRCM signals, DMA
requests, and interrupts) to be routed to the pins dedicated to the hardware debug.
The first layer is in the CORE power domain. It is controlled by the core control module registers and
selects the set of internal signals from the CORE power domain to be routed. The second layer is in the
WKUP power domain. It is controlled by the wake-up control module registers and selects the set of
internal signals from the WKUP power domain.
The pads used for the hardware debug must be properly configured by selecting the hardware debug
function (hw_dbgn) of the pad. To configure the pads, select mode 5 (0b101) in the MUXMODE bit field of
the CONTROL.CONTROL_PADCONF_CAM_x register (only for hw_dbg0 to hw_dbg11), or select mode 7
(0b111) in the MUXMODE bit field of the CONTROL.CONTROL_PADCONF_ETK_x register (for all
hw_dbgn). Before selecting the CORE signals, the WKUPOBSMUX bit field of the
CONTROL.CONTROL_WKUP_DEBOBS_n registers must be set to 0.
Table 13-29. Observability Registers
Physical
Register Name
Description
Access
Address
Device Type
E/T/G
S/B
0x4800 2420
Set and configure CORE observable signals 1
R/W
R
and 0.
0x4800 2424
Set and configure CORE observable signals 3
R/W
R
and 2.
0x4800 2428
Set and configure CORE observable signals 5
R/W
R
and 4.
2486System Control Module
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
