Public Version
www.ti.com
Display Subsystem Register Manual
Bits
Field Name
Description
Type
Reset
23
VIDARBITRATION
Determines the priority of the video pipeline. The video pipeline is
RW
0
one of the high priority pipeline. The arbitration wheel gives always
the priority first to the high priority pipelines using round-robin
between them. When there is only normal priority pipelines sending
requests, the round-robin applies between them.
0x0:
The video pipeline is one of the normal priority pipeline.
0x1:
The video pipeline is one of the high priority pipeline.
22
VIDLINEBUFFER
Video vertical line buffer split
RW
0
SPLIT
0x0:
Vertical line buffers are not split.
0x1:
Vertical line buffers are split into two.
21
VIDVERTICALTAPS
Video vertical resize tap number
RW
0
0x0:
Three taps are used for the vertical filtering logic. The
other two taps are not used.
0x1:
Five taps are used for the vertical filtering logic.
20
VIDDMAOPTI
Video optimization in case of
RW
0
MIZATION
0x0:
The DMA engine fetches one pixel for each 32-bit OCP
request (RGB16 and YUV422) while doing 90- and
270-degree rotation (accessing on-chip memory and
off-chip memory).
0x1:
The DMA engine fetches two pixels for each 32-bit OCP
request (RGB16 and YUV422) while doing 90- and
270-degree rotation (accessing on-chip memory and
off-chip memory).
The bit field [21] VIDVERTICALTAPS shall be set to 0x1,
bit field [22] VIDLINEBUFFERSPLIT to 0x1, and all scaler
registers shall be configured even for 1:1 ratio.
Even width is required for the input picture when 5 taps are
used.
19
VIDFIFOPRELOAD
Video preload value
RW
0
0x0:
H/W prefetches pixels up to the preload value defined in
the preload register.
0x1:
H/W prefetches pixels up to the high threshold value.
18
VIDROWREPEAT
Video Row Repeat (YUV case only when rotating 90 or
RW
0
ENABLE
270-degree)
0x0:
Row of VIDn won't be read twice.
0x1:
The Row data are fetched twice to extract both the Y
components
17
VIDENDIANNESS
Video Endianness
RW
0
0x0:
Little endian operation is selected.
0x1:
Big endian operation is selected.
16
VIDCHANNELOUT
Video Channel Out configuration
RW
0
wr: Immediate
0x0:
LCD output selected
0x1:
24 bit output selected
15:14
VIDBURSTSIZE
Video DMA Burst Size
RW
0x0
0x0:
4x32bit bursts
0x1:
8x32bit bursts
0x2:
16x32bit bursts
0x3:
Reserved
13:12
VIDROTATION
Video Rotation Flag
RW
0x0
0x0:
No rotation or VidFormat is RGB
0x1:
Rotation by 90 degrees
0x2:
Rotation by 180 degrees
0x3:
Rotation by 270 degrees
1853
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
