Public Version
McBSP Integration
www.ti.com
Table 21-4. Software Reset Signals to All McBSP Modules (continued)
Type
Bit Field
Register Source
Activation
Description
FRST
MCBSPi.
[7]
Frame-sync logic is reset. Frame-sync
generated signal is not generated by
the SRG
For more details about these signals, see
, McBSP Register Manual. See
McBSP Initialization Procedure, for a complete description of the McBSP initialization procedure.
21.3.2.4 Power Management
21.3.2.4.1 McBSP Operating States
Two operating states are defined for all the McBSP modules:
•
ACTIVE state: The module is running synchronously on the interface and functional clock, interrupts
and DMA requests can be generated according to the configuration (register, master or slave mode,
etc) and the external signals.
•
IDLE state: As part of the system power management, the PRCM module can request the McBSP
modules to enter IDLE state. Depending on the configured acknowledgment mode: Force Idle, No Idle
and Smart Idle modes, a McBSP module will effectively enter IDLE state or not. As soon as a McBSP
module enters IDLE state, it doesn't have anymore activities except those unrelated to clock activity
(for example wake-up features) and its clocks are likely to be switched off at PRCM level.
When the McBSP goes into IDLE state, the McBSP internal state-machine clock switches from
interface clock (L4_ICLK) to external serial clock (because OMAP is supposed to shut down all internal
clocks). Then the McBSP can continue to process during IDLE state with the external clock provided
by the external component/AUDIOBUFFER.
The McBSP can exit IDLE state only if the external serial clock is active. After exiting IDLE state,
McBSP state-machine clock is provided by the OMAP interface clock (L4_ICLK).
NOTE:
Idle request and idle acknowledge are only internal signals, with no means to observe or to
control. The signals generation and control is purely hardware (managed automatically by
the PRCM and the McBSP module depending on the SIDLEMODE settings).
21.3.2.4.2 McBSP Acknowledgment Modes
During initialization or configuration of the McBSP module, the software must configure how the McBSP
module will answer an IDLE solicitation from the PRCM module ( that is, the way idle acknowledge will be
asserted following an idle request assertion).
Each McBSP module can be configured via the MCBSPi.
[4:3]
SIDLEMODE field as one of the following acknowledgment modes:
•
Force Idle mode (SIDLEMODE bit = 0x0): An idle request is acknowledged unconditionally, regardless
of the internal state of the module. The McBSP module immediately enters Idle state (no activity),
interface and PRCM functional clock can be stopped, no interrupts and DMA requests can be
generated. In this mode, the McBSP module freezes all the internal activity when the PRCM clocks are
switched off by the PRCM module, leading to a potential loss of data.
CAUTION
In Force Idle mode, the wake-up feature is inhibited.
3080
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
