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PRCM Basic Programming Model
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The voltage processor picks up the voltage step and the waiting time among the minimum and maximum
values depending on the VDD returned by the error to the voltage controller.
3.6.5.3.4 PRM_VP_VLIMITTO (Voltage Processor Voltage Limit and Time-Out)
This register allows setting the following:
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The minimum allowed voltage value
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The maximum allowed voltage value
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The time-out value (in the number of clock cycles) to wait for an update
The device has the following voltage processor configuration registers:
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3.6.5.3.5 PRM_VP_VOLTAGE (Voltage Processor Voltage Register)
The voltage register in the voltage processor indicates the current value of the power IC device voltage.
This register is updated only when the voltage processor sends the update command to the voltage
controller.
The device has the following voltage processor voltage registers:
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3.6.5.3.6 PRM_VP_STATUS (Voltage Processor Status Register)
The status register in the voltage processor indicates whether the voltage processor is in idle mode. This
information is useful before trying to reprogram the voltage processor. Unlike other voltage processor
status events logged as a source of an interrupt on the MPU, the event logged in this register is not a
cause of the interrupt.
The device has the following voltage processor status registers:
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3.6.6 Generic Programming Examples
3.6.6.1
Clock Control
The module clock management is controlled through three programmable steps:
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Enabling or disabling the functional clocks
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Enabling or disabling the interface clocks
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Enabling or disabling the automatic idle mode for the interface clocks
3.6.6.1.1 Enabling and Disabling the Functional Clocks
The flow chart in
shows how to enable or disable a functional clock.
The first step before enabling a functional clock is to select the proper source clock using the
corresponding clock selection register (CM_CLKSEL_<domain_name>). It can be either an external
source clock or an internal clock; that is, sys_altclk or DPLL4_M3_CLK for the DSS_TV_FCLK functional
clock of the DSS.
If the source clock is a DPLL3 or DPLL4 output clock, the DPLL multiplier, divider, and output clock ratios
are set in the CM_CLKSELn_PLL register, where n is from 1 to 3. The DPLL operating mode is set in the
register.
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Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
