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General-Purpose Timers
16.2.6.1.2 Write Nonposting Synchronization Mode
This mode is used if the GPTi.
[2] POSTED bit is set to 0.
This mode uses a nonposted write scheme to update any internal register. Therefore, the write transaction
is not acknowledged on the L4 interface until the effective write operation occurs after the
resynchronization in the timer functional clock domain. The drawback is that both the interconnect and the
device that requested the write transaction are stalled during this period.
The same full resynchronization scheme is used for a read transaction, and the same stall period applies.
A register read following a write to the same register is always coherent.
This mode is functional regardless of the ratio between the L4 interface frequency and the timer clock
frequency.
16.2.6.2 Reading From Timer Counter Registers
In 16-bit access mode, reading the 16 LSBs from the timer counter registers (GPTi.
, GPTi.
and GPTi.
) captures the current timer counter value. This must be followed by reading the
16MSBs.
IVA2.2 subsystem 16-bit accesses can be interleaved with MPU subsystem 32-bit accesses.
NOTE:
LSB/MSB accesses cannot be interleaved (that is, the sequence LSB register 1, LSB
register 2, MSB register 1, MSB register 2 is not supported).
2723
SWPU177N – December 2009 – Revised November 2010
Timers
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