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Display Subsystem Basic Programming Model
•
DSS.
•
DSS.
•
DSS.RFBI_CONFIG0 (configuration 0) and DSS.RFBI_CONFIG1 (configuration 1)
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DSS.
•
DSS.
The configuration register for one configuration can be accessed only when the configuration is not in use
(based on the value of the
[3:2] CONFIGSELECT bit field).
7.5.7.3.1 Parallel Mode
The DSS.
[1:0]PARALLELMODE bit field (where i = 0, 1) defines the width of the interface
(8-, 9-, 12-, or 16-bit parallel).
7.5.7.3.2 Trigger Mode
Setting the DSS.RFBI_CONFIG[3:2]TRIGGERMODE bit field configures the trigger on the external TE
signal (RFBI_TE_VSYNC), or external with VSYNC/HSYNC with the programmable number of HSYNCs to
begin the transfer in both cases or the internal programmable DSS.
[4] ITE bit.
7.5.7.3.3 VSYNC Pulse Width (Minimum Value)
The DSS.
[15:0] MINVSYNCPULSEWIDTH bit field defines the minimum number of
L4 clock cycles of the VSYNC pulse for detection on VSYNC. It allows differentiation between VSYNC and
HSYNC, which are ORed on the same signal and is also used in the VSYNC/HSYNC mode on the two
separate input lines.
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The VSYNC pulse width must be at least equal to two L4 cycles when HSYNC is not present.
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The VSYNC pulse width must be at least equal to four L4 cycles when HSYNC is present.
7.5.7.3.4 HSYNC Pulse Width (Minimum Value)
The DSS.
[15:0] MINHSYNCPULSEWIDTH bit field defines the minimum number of
L4 clock cycles of the HSYNC pulse for detection on HSYNC. It allows differentiation between VSYNC
and HSYNC, which are ORed on the same signal, and is also used in the VSYNC/HSYNC mode on the
separate two input lines. The HSYNC pulse width must always be at least equal to two L4 cycles to be
detected.
7.5.7.3.5 Cycle Format
Setting the DSS.
[10:9] CYCLEFORMAT bit field (with i = 0, 1) defines which registers are
used to format the data in the interconnect FIFO with the appropriate number of bits (starting from the
LSB) and with the alignment on the interface as follows:
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DSS.RFBI_DATA_CYCLE_i (if DSS.RFBI_CONFIG[10:9] CYCLEFORMAT bit field = 00) only
or
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DSS.
and DSS.
(if DSS.RFBI_CONFIG[10:9]
CYCLEFORMAT bit field = 01)
or
•
DSS.
, DSS.
(if
DSS.RFBI_CONFIG[10:9] CYCLEFORMAT bit field = 10)
The data from the display controller and from the L4 interconnect are formatted based on the configuration
of the DSS.RFBI_DATA_CYCLE_i registers.
7.5.7.3.6 Unused Bits
Based on the configuration, the undefined bits for each cycle are defined with the previous values of the
bits at the same position in the previous cycle, 0s, or 1s (the unused bits can be at any position). The
DSS.
[12:11] UNUSEDBITS bit field (with i = 0, 1) is used.
1767
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
