@GPIO_IRQENABLEx
register
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
@GPIO_IRQENABLEx
register
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
Write
@GPIO_SETIRQENABLEx
(0b1000 0000 0000 1110)
gpif-011
Public Version
General-Purpose Interface Basic Programming Model
www.ti.com
25.5.2.3.2 Set Instruction Example
Assume the interrupt-enable1 (or enable2) register (or the data output register) contains the binary value,
0b0000 0001 0000 0000, and you want to set bits 15, 3, 2, and 1.
With the set instruction feature, write 0b1000 0000 0000 1110 at the address of the set interrupt-enable1
(or enable2) register (or at the address of the set data output register). After this write operation, a reading
of the interrupt-enable1 (or enable2) register (or the data output register) returns 0b1000 0001 0000 1110;
bits 15, 3, 2, and 1 are set.
NOTE:
Although the general-purpose interface registers are 32 bits wide, only the less-significant
16 bits are represented in this example.
shows an example of a set instruction.
Figure 25-11. Write @GPIO_SETIRQENABLEx Register Example
The set wakeup-enable register offers the same feature with the wakeup-enable register.
25.5.3 Interrupt and Wakeup
25.5.3.1 Involved Configuration Registers
•
Interrupt-enable registers (GPIOi.
and GPIOi.
The interrupt-enable1 (or interrupt-enable2) register allows masking of the expected transition on input
GPIO to prevent the generation of an interrupt request on line1 (or line2). The interrupt-enable
registers are programmed synchronously with the interface clock.
These registers can be accessed with direct read/write operations or using the alternate set-and-clear
protocol register update feature. This feature enables to set or clear specific bits of these registers with
a single write access to the corresponding set interrupt-enable1 (or interrupt-enable2) registers (or to
the clear interrupt-enable1 [or interrupt-enable2] registers) address (see
, Set and Clear
Instructions).
•
Wakeup-enable register (GPIOi.
The wakeup-enable register allows masking of the expected transition on input GPIO to prevent the
generation of a wake-up request. The wakeup-enable register is programmed synchronously with the
interface clock before any idle mode request coming from the host processor.
This register can be accessed with direct read/write operations or by using the alternate set-and-clear
protocol register update feature. This feature allows setting or clearing specific bits of this register with
a single write access to the set wakeup-enable register (or to the clear wakeup-enable register)
address (see
, Set and Clear Instructions).
NOTE:
There must be a correlation between wakeup-enable and interrupt-enable registers. If a
GPIO pin has a wakeup configured on it, it should also have the corresponding interrupt
enabled (on one of the two interrupt lines). Otherwise, it is possible to have a wake-up event,
but after exiting the Idle mode, no interrupt is generated, thus the corresponding bit from the
interrupt-status register is not cleared, and the module does not acknowledge a future IDLE
request.
3482
General-Purpose Interface
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
