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General-Purpose Interface Basic Programming Model
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25.5 General-Purpose Interface Basic Programming Model
25.5.1 Power Saving by Grouping the Edge/Level Detection
Each GPIO module implements four gated clocks used by the edge/level detection logic to save power.
Each group of eight input GPIO pins generates a separate enable signal depending on the edge/level
detection register setting (because the input is 32 bits, four groups of eight inputs are defined for each
GPIO module). If a group requires no edge/level detection, then the corresponding clock is gated (cut off).
Grouping the edge/level enable can save the power consumption of the module as described in the
following example.
If any of the following registers
•
GPIOi.
•
GPIOi.
•
GPIOi.
•
GPIOi.
are set to 0x01 01 01 01, all clocks are active (power consumption is high). If any of these registers are
set to 0x00 00 00 FF, only one clock is active (power saving).
NOTE:
When the clocks are enabled by writing to the GPIOi.
, and
registers, the detection starts after five clock cycles. This
period is required to clean the synchronization edge/level detection pipeline.
The mechanism is independent of each clock group. If the clock was started before and a
new setting is performed, the following is recommended: First, set the new detection
required; second, disable the previous setting (if necessary). In this way, the corresponding
clock is not gated and the detection starts immediately.
25.5.2 Set and Clear Instructions
25.5.2.1 Description
GPIO implements the set-and-clear protocol register update for the GPIOi.
,
, GPIOi.GPIO_ IRQENABLE2, and GPIOi.
registers.
This protocol is an alternative to the atomic test and set operations and consists of writing operations at
dedicated addresses (one address for setting bit[s] and one address for clearing bit[s]). The data to write
is 1 at bit position(s) to clear (or to set) and 0 at unaffected bit(s). Registers can be accessed in two ways:
•
Standard: Full register read and write operations at the primary register address
•
Set and clear (recommended): Separate addresses are provided to set (and clear) bits in registers.
Writing 1 at these addresses sets (or clears) the corresponding bit into the equivalent register; writing a
0 has no effect.
Therefore, for these registers, three addresses are defined for one unique physical register. Reading these
addresses has the same effect and returns the register value.
25.5.2.2 Clear Instruction
25.5.2.2.1 Clear Register Addresses
Clear interrupt-enable registers (GPIOi.
and
).
A write operation in the clear interrupt-enable1 (or enable2) register clears the corresponding bit in the
interrupt-enable1 (or enable2) register when the written bit is 1; a written bit at 0 has no effect.
A read of the clear interrupt-enable1 (or enable2) register returns the value of the interrupt-enable1 (or
enable2) register.
Clear wakeup-enable register (GPIOi.
3480
General-Purpose Interface
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
