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IVA2.2 Subsystem Functional Description
generation (IVA2.2_MSTANDBY signal in
) to the PCRM. Using the signals
DSP_MEGACELL_STANDBY, EDMA_STANDBY, VIDEO_STANDBY, Mx_IdleReq, and Mx_IdleAck, the
SYSC manages and controls the correct power-down transition of the IVA2.2 subsystem and its
submodules to ensure that the IVA2.2 internal clocks can be cut. For information about the IVA2.2
power-down transition and its programming model, see
, Power-Down and Wake-Up
Management.
External events can also occur at the IVA2.2 boundary (access to IVA2.2 using the slave access port or
external nonmasked events), requiring the restart of the IVA2.2 clocks (in case of IVA2.2 standby state).
The WUGEN module controls the asynchronous generation of a wake-up signal to the PRCM; this signal
restarts IVA2.2 PLL clock generation, allowing the SYSC to regenerate the IVA2.2 internal clocks.
5.3.7.3
Boot Configuration
The IVA_SYSC.
and IVA_SYSC.
registers are the boot-time
configuration registers. These read-only registers are accessible only by the DSP, and their values are
determined when the IVA2.2 subsystem is released from reset by the PRCM.
The values of these registers are driven externally by two system control module registers,
SYSC_GENERAL1.CONTROL_IVA2_BOOTADDR and
SYSC_GENERAL1.CONTROL_IVA2_BOOTMOD, which are read-write accessible by the MPU
subsystem for MPU-driven IVA2.2 boot sequence and/or by the IVA2.2 DSP for autonomous boot. For
more information, see
, IVA2.2 Boot.
NOTE:
If the values of the SYSC_GENERAL1.CONTROL_ IVA2_BOOTADDR and
SYSC_GENERAL1.CONTROL_IVA2_BOOTMOD registers change, the new
IVA2.2.
and IVA2.2.
register values are not updated
until the next reset.
For more information, see
, IVA2.2 Boot.
5.3.7.4
Interconnect Optimization
The IVA2.2.
and IVA2.2.
registers are local interconnect configuration
registers. They are read-write accessible by the DSP only. Setting these registers enables or disables
interconnect optimization.
5.3.7.5
Video Accelerator/Sequencer SYSC
The video and sequencer system control module (called VIDEOSYSC in
, Video System
Controller Registers) controls module reset, power management, and interrupt handling for the video
accelerators/sequencer modules.
5.3.7.5.1 Reset
The reset module resynchronizes asynchronous reset for the following modules:
•
iVLCD
•
iME
•
iLF
•
SL2IF
•
Video and sequencer interconnect
•
Sequencer
For details, see
, IVA2.2 Subsystem Integration.
5.3.7.5.2 Power Management
The video accelerator/sequencer SYSC controls clock gating for the iLF, iME, iVLCD, and sequencer
modules and controls clock division for the sequencer module.
739
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
