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General-Purpose Timers Register Manual
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16.3 General-Purpose Timers Register Manual
16.3.1 GP Timer Register Map
16.3.1.1 Instance Summary
lists the base address and block size for the GP timer module instances. All timers are
memory mapped to the L4 peripheral bus memory space.
Table 16-12. GP Timer Instance Summary
Module Name
Base Address
Size
GPTIMER1
0x4831 8000
4K bytes
GPTIMER2
0x4903 2000
4K bytes
GPTIMER3
0x4903 4000
4K bytes
GPTIMER4
0x4903 6000
4K bytes
GPTIMER5
0x4903 8000
4K bytes
GPTIMER6
0x4903 A000
4K bytes
GPTIMER7
0x4903 C000
4K bytes
GPTIMER8
0x4903 E000
4K bytes
GPTIMER9
0x4904 0000
4K bytes
GPTIMER10
0x4808 6000
4K bytes
GPTIMER11
0x4808 8000
4K bytes
16.3.2 GP Timer Register Mapping Summary
CAUTION
The GP timer registers are limited to 32-bit and 16-bit data accesses; 8-bit
access is not allowed and can corrupt the register content.
through
provide the register summary and associated offset addresses for the 11
GP timer internal registers. (Example: The physical address for the
register of GPTIMER8 is
0x4903 E024.)
2724Timers
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated