Texas Instruments OMAP36 Series, Technical Reference Manual

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SDRAM Controller (SDRC) Subsystem
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Bits Field Name Description Type Reset
11:9 CS0MUXCFG Identifies the SDRC pins used by CS0 RW See
(1)
0x0: 32-bit SDRAM on Datalane[31:0]
0x1: 32-bit SDRAM on Datalane[31:0]
0x2: 16-bit SDRAM on Datalane[31:16]
0x3: 16-bit SDRAM on Datalane[16:0]
0x4: Reserved
0x5: Reserved
0x6: Reserved
0x7: 16-bit SDRAM on Datalane[31:16]
8 SDRCTRISTATE Static 3-state command for the SDRC I/O pads RW See
(1)
0x0: All SDRC interface pins are set to hi-Z.
0x1: Normal mode: SDRC drives the I/O pads based on the memory
traffic.
7:0 RESERVED Write 0s for future compatibility. Read returns 0s. RW See
(1)
Table 10-162. Register Call Summary for Register SDRC_SHARING
SDRAM Controller (SDRC) Subsystem
• CS0-CS1 Memory Spaces : [0] [1]
• Data Multiplexing During Write Operations : [2] [3] [4]
• Data Demultiplexing During Read Operations : [5] [6]
• Memory Configuration : [7] [8]
• SDRC Register Summary : [9]
Table 10-163. SDRC_ERR_ADDR
Address Offset 0x0000 0048
Physical Address 0x6D00 0048 Instance SDRC
Description This register captures the address of the last illegal access received on the interconnect.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRORADDRESS
Bits Field Name Description Type Reset
31:0 ERRORADDRESS Address of illegal access (Bit 31 is always 0.) R 0x00000000
Table 10-164. Register Call Summary for Register SDRC_ERR_ADDR
SDRAM Controller (SDRC) Subsystem
• Error Management : [0]
• SDRC Register Summary : [1]
2318 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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