Texas Instruments OMAP36 Series, Technical Reference Manual

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128M-byte address space
128M-byte address space
128M-byte address space
128M-byte address space
128M-byte address space
128M-byte address space
128M-byte address space
128M-byte address space
CS0 start address slot fixed interconnect address 0
CS1 start address slot defined by
SDRC_CS_CFG[9:8] CS1STARTLOW and
SDRC_CS_CFG[3:0] CS1STARTHIGH
CS1 SDRAM
address space
Illegal address space - Accessing this address
range generates an error
CS0 SDRAM
address space
1 Gbyte SDRC
address space -
8 partitions
sdrc-011
CS1 max
(depends on
SDRC_MCFG_1[17:8] RAMSIZE)
CS0 max (depends on
SDRC_MCFG_0[17:8] RAMSIZE)
Public Version
SDRAM Controller (SDRC) Subsystem
www.ti.com
Figure 10-51. CS0/CS1 Chip-Select Start Address Slots
10.2.4.4.1.3 SDRAM Memory Combinations on CS1 and CS0
The combinations of SDR and DDR memories/SDRAMs are defined as follows:
• SDR and DDR memories can be connected on either CS1 or CS0.
• The only restriction on the coexistence of SDRAMs on CS0 or CS1 is that a combination of SDR on
one CS and DDR on the other CS is not allowed.
The SDRAM data bus width on each CS is determined by the SDRC. SDRC_SHARING [11:9]
CS0MUXCFG and SDRC. SDRC_SHARING [14:12] CS1MUXCFG fields of the memory-sharing registers.
10.2.4.4.2 Bank Tracking
The main state-machine controls all the accesses to external memories.
The SDRC contains hardware for tracking open pages on a per-bank basis. Up to four open pages are
tracked per CS, for a maximum of eight open pages tracked.
To pipeline accesses efficiently, the SDRC includes a request look-ahead FIFO that analyzes interconnect
requests with respect to the status of the target banks. A bank status can be any of the following:
• Bank open on another row
• Bank closed
• Bank open on the same row
The SDRC state-machine generates the appropriate sequence of memory commands. All precharge and
active commands are hidden as much as possible, to optimize the memory bandwidth usage.
The look-ahead FIFO depth is 9 * 64-bit requests, with a limit of four different transactions. As soon as the
look-ahead FIFO stores four complete transactions or when it is full, the SCmdAccept is deasserted and
any incoming request is blocked.
2248 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated