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SDRAM Controller (SDRC) Subsystem
Bits
Field Name
Description
Type
Reset
31:10
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x000000
9:8
CS1STARTLOW
CS1 address space start address (lower add bits a1:a0) / 32MB unit
RW
0x0
7:4
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x0
3:0
CS1STARTHIGH
CS1 address space start address (upper add bits a5:a4:a3:a2) / 128MB
RW
0x4
unit
Table 10-160. Register Call Summary for Register SDRC_CS_CFG
SDRAM Controller (SDRC) Subsystem
•
•
:
•
[7] [8] [9] [10] [11] [12] [13]
•
Table 10-161. SDRC_SHARING
Address Offset
0x0000 0044
Physical Address
0x6D00 0044
Instance
SDRC
Description
This register specifies the SDRC attached memory size and position on the SDRC IOs.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
LOCK
RESERVED
CS1MUXCFG
CS0MUXCFG
SDRCTRISTATE
Bits
Field Name
Description
Type
Reset
31
RESERVED
Write 0s for future compatibility.
RW
0x0
Read returns 0.
30
LOCK
Read-only access lock bit
RW
See
(1)
0x0: This register is fully writable.
0x1: When this bit is set, the register can not be unset until next reset
of the module.
29:15
RESERVED
Write 0s for future compatibility.
RW
See
(1)
Read returns 0s.
14:12
CS1MUXCFG
Identifies the SDRC pins used by CS1
RW
See
(1)
0x0: 32-bit SDRAM on Datalane[31:0]
0x1: 32-bit SDRAM on Datalane[31:0]
0x2: 16-bit SDRAM on Datalane[31:16]
0x3: 16-bit SDRAM on Datalane[16:0]
0x4: Reserved
0x5: Reserved
0x6: Reserved
0x7: 16-bit SDRAM on Datalane[31:16]
(1)
Reset value is copied from the system control module. See the note in
and
, SDRC Registers, in
, System Control Module.
2317
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
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