Texas Instruments OMAP36 Series, Technical Reference Manual

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SDRAM Controller (SDRC) Subsystem
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Table 10-151. SDRC Instance Summary
Module Name Base Address Size
SDRC 0x6D00 0000 64K bytes
10.2.8.2 SDRC Register Summary
Table 10-152 summarizes the SDRC register mapping.
Table 10-152. SDRC Register Summary
Register Name Type Register Width (Bits) Address Offset Physical Address
SDRC_REVISION R 32 0x0000 0000 0x6D00 0000
SDRC_SYSCONFIG RW 32 0x0000 0010 0x6D00 0010
SDRC_SYSSTATUS R 32 0x0000 0014 0x6D00 0014
SDRC_CS_CFG RW 32 0x0000 0040 0x6D00 0040
SDRC_SHARING RW 32 0x0000 0044 0x6D00 0044
SDRC_ERR_ADDR R 32 0x0000 0048 0x6D00 0048
SDRC_ERR_TYPE RW 32 0x0000 004C 0x6D00 004C
SDRC_DLLA_CTRL RW 32 0x0000 0060 0x6D00 0060
SDRC_DLLA_STATUS R 32 0x0000 0064 0x6D00 0064
SDRC_POWER_REG RW 32 0x0000 0070 0x6D00 0070
SDRC_MCFG_p
(1)
RW 32 0x0000 0080 0x6D00 0080
+ (0x0000 0030 * p) + (0x0000 0030 * p)
SDRC_MR_p
(1)
RW 32 0x0000 0084 0x6D00 0084
+ (0x0000 0030 * p) + (0x0000 0030 * p)
SDRC_EMR2_p
(1)
RW 32 0x0000 008C 0x6D00 008C
+ (0x0000 0030 * p) + (0x0000 0030 * p)
SDRC_ACTIM_CTRLA_p
(1)
RW 32 0x0000 009C 0x6D00 009C
+ (0x0000 0028 * p) + (0x0000 0028 * p)
SDRC_ACTIM_CTRLB_p
(1)
RW 32 0x0000 00A0 0x6D00 00A0
+ (0x0000 0028 * p) + (0x0000 0028 * p)
SDRC_RFR_CTRL_p
(1)
RW 32 0x0000 00A4 0x6D00 00A4
+ (0x0000 0030 * p) + (0x0000 0030 * p)
SDRC_MANUAL_p
(1)
RW 32 0x0000 00A8 0x6D00 00A8
+ (0x0000 0030 * p) + (0x0000 0030 * p)
(1)
p = 0 to 1.
10.2.8.3 SDRC Register Description
This section provides a description of SDRC registers.
Table 10-153. SDRC_REVISION
Address Offset 0x0000 0000
Physical Address 0x6D00 0000 Instance SDRC
Description This register contains the IP revision code. This code is specified at design time.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REV
2314 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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