Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2297 / 3738

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SDRAM Controller (SDRC) Subsystem
• Maximum number of columns = 10 (number of address lines used for column decoding)
Total locations in a bank = (2
13
) * (2
10
) (32)
Then calculate the total locations in the device:
Total locations in the device = (Number of banks) * (Total locations in a bank) = (2
2
) * (2
13
* 2
10
) = 2
25
(33)
Finally calculate the SDRAM device capacity:
Total device capacity = (Total locations in the device) *(Device organization) = (2
25
) * (16) = 2
29
bits (34)
Hence, the device has a maximal capacity of 512M bits (or 64M bytes).
In the same way, the SDRC maximal capacity can be calculated as follow:
• Number of address lines: 15 (A0-A14)
• Maximum number of rows = 15 (limited by the number of address lines, hence do not program
SDRC_MCFG_p [26:24] RASWIDTH above 15)
• Maximum number of columns = 12 (limited by SDRC_MCFG_p [22:20] CASWIDTH)
• Data bus width to external device: 32-bit
SDRC total capacity = (2
15
* 2
12
) * 32 = 4G bits (or 512M bytes) (35)
Hence, the SDRC has a maximum addressing capability of 8G bits/1G byte (as seen in
Section 10.2.6.3.1.1 ) and can manage SDRAM devices with capacity of up to 4G bits/512M bytes (see the
following Caution).
CAUTION
Because the SDRC is aligned on the JEDEC LPDDR1 SDRAM standard, it is
guaranteed that SDRAM with up to 2-Gbit capacity are supported. At the time
of writing, 4-Gbit low-power DDR SDRAM is not yet in production, and
depending on its design (that is, the number of banks, page size, and other
characteristics) this SDRAM may or may not be supported by the SDRC.
10.2.6.3.2.2 CS Size
Each chip-select has its programmable size. The CS size is expressed in SDRC_MCFG_p [17:8]
RAMSIZE (p = 0 or 1 for CS0 or CS1) as a number of 2M-byte chunks.
For instance, when connecting a 256M-bit SDRAM memory (see the mux scheme MUX7 in Table 10-96 )
to the SDRC controller, RAMSIZE must be set with the value 0x010 (32M bytes = 2MB * 16).
10.2.6.3.2.3 CS Start and End Addresses
See Figure 10-77 , CS0/CS1 Chip-Select Start Address Slots, for a graphical representation of CS starts
addresses and CS size.
CS0 start address is fixed at :
• 0x0000 0000 from an SDRC point of view
• 0x8000 0000 from a global memory space point of view.
Therefore, when connecting a 256M bit/32M-byte SDRAM memory (16M * 8 such as in MUX6,
Table 10-96 ), the CS0 end address is 0x0200 0000 (SDRC point of view).
CS1 start address is programmable and its default value is :
• 0x2000 0000 from an SDRC address point of view
• 0xA000 0000 from a global memory space point of view.
The SDRC 1G-byte address space is segmented into eight 128M-byte address spaces, which are
themselves segmented into four 32M-byte address spaces so that 32 possible CS1 start address locations
are defined, as shown in
Figure 10-77 . The first 32M-byte address space of the first 128M-byte address
space is reserved for CS0 (address 0x0000 0000). Any other address can be used as the CS1 start
address. To define a CS1 start address, set the
SDRC_CS_CFG [9:8] CS1STARTLOW and
SDRC_CS_CFG [3:0] CS1STARTHIGH fields as follows:
2297 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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