Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2229 / 3738

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SDRAM Controller (SDRC) Subsystem
Table 10-96. SDRC Address Multiplexing Scheme Selection vs SDRAM Configurations (x16
Memory Interface)
x16 Memory Interface
Banks Column Row MUX Total Size Number of Device
Address Address Scheme (MBits) Devices Organization
BA0 1 A0-A7 8 A0-A10 11 MUX1 16 1 1M x 16
BA0 1 A0-A7 8 A0-A11 12 MUX2 32 1 2M x 16
BA1, 2 A0-A7 8 A0-A11 12 MUX2 64 1 4M x 16
BA0
BA1, 2 A0-A8 9 A0-A11 12 MUX4 128 2 8M x 8
BA0
1 8M x 16
BA1, 2 A0-A8 9 A0-A12 13 MUX7 256 1 16M x 16
BA0
BA1, 2 A0-A8 9 A0-A13 14 MUX26 512 1 32M x 16
BA0
BA1, 2 A0-A9 10 A0-A11 12 MUX6 256 2 16M x 8
BA0
1 16M x 16
BA1, 2 A0-A9 10 A0-A12 13 MUX10 512 2 32M x 8
BA0
10 1 32M x 16
BA1, 2 A0-A9 10 A0-A13 14 MUX13 1024 1 64M x 16
BA0
BA1, 2 A0-A9; A11 11 A0-A12 13 MUX12 1024 2 64M x 8
BA0
1 64M x 16
Table 10-97. SDRC Address Multiplexing Scheme Selection vs SDRAM Configurations (x32
Memory Interface)
x32 Memory Interface
Banks Column Row MUX Total Size Number of Device
Address Address Scheme (MBits) Devices Organization
BA0 1 A0-A7 8 A0-A11 12 MUX5 64 2 2M x 16
1 2M x 32
BA1, 2 A0-A7 8 A0-A10 11 MUX3 64 1 2M x 32
BA0
BA1, 2 A0-A7 8 A0-A11 12 MUX5 128 1 4M x 32
BA0
BA1, 2 A0-A7 8 A0-A12 13 MUX9 256 1 8M x 32
BA0
BA1, 2 A0-A7 8 A0-A13 14 MUX27 512 1 16M x 32
BA0
BA1, 2 A0-A7 8 A0-A14 15 MUX28 1024 1 32M x 32
BA0
BA1, 2 A0-A8 9 A0-A11 12 MUX8 256 4 8M x 8
BA0
2 8M x 16
1 8M x 32
BA1, 2 A0-A8 9 A0-A12 13 MUX24 512 1 16M x 32
BA0
BA1, 2 A0-A8 9 A0-A13 14 MUX23 1024 1 32M x 32
BA0
BA1, 2 A0-A8 9 A0-A14 15 MUX25 2048 1 64M x 32
BA0
2229 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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