128M-byte address space
32M-byte address space
32M-byte address space
32M-byte address space
32M-byte address space
CS0 start address slot
fixed interconnect address 0x0000 0000
CS1 start address slot defined by
SDRC_CS_CFG[9:8] CS1STARTLOW = 0x00 and
SDRC_CS_CFG[3:0] CS1STARTHIGH = 0x0100
Illegal address space - Accessing this address
Illegal address space - Accessing this address
range generates an error
range generates an error
CS0 SDRAM 256Mb / 32 MB address space
1 Gbyte SDRC
address space
8 partitions
sdrc-041
CS1 max address, defined by
SDRC_MCFG_1[17:8] RAMSIZE = 0x80
CS0 max address, defined by
SDRC_MCFG_0[17:8] RAMSIZE = 0x010
0x2000 0000
0x4000 0000
0x0000 0000
0x3000 0000
0x0200 0000
CS1 SDRAM 2048Mb / 256MB address space
Public Version
SDRAM Controller (SDRC) Subsystem
www.ti.com
•
[3:0] CS1STARTHIGH corresponds to one of the eight 128M-byte address spaces
(total address space of SDRC is 1G-byte): 0x0000 for the first partition up to 0x0111 for the eights
partition. The
[3] must always be set to 0.
•
[9:8] CS1STARTLOW corresponds, for a given 128M-byte address space, to one of
the four 32M-byte address spaces: 0x00 for the first, up to 0x11 for the fourth.
Therefore, for a start address of 0x2000 0000 (SDRC point of view) when connecting a 2048-Mbit SDRAM
memory (64M * 32 such as in MUX25,
), the
[9:8] CS1STARTLOW bit field
must be set to 0x00 (the first 32M-byte address space, as shown in
), and the
[3:0] CS1STARTHIGH bit field must be set to 0x0100 (fourth 128M-byte address space).
The start address must be aligned on the memory size.
The CS1 end address (0x3000 0000) can be deduced from the CS1 size ( that is, from the RAMSIZE
parameter), which takes the value 0x80 when connecting a 2048-Mbit SDRAM memory.
Figure 10-77. CS Start and End Address Configuration Example
10.2.6.4 How to Choose a Suitable SDRAM
This section describes how to select a suitable SDRAM device to interface with the SDRC controller.
Basically, if an SDRAM device is aligned with the JEDEC LPDDR1 SDRAM standard (JEDEC committee
JC42.3), the SDRAM device is likely to be compatible with the SDRC controller. To ensure that an
SDRAM device is fully compatible, see the following sections.
2298
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated