sdrc-037
Virtual address
space 1 (Q3)
Virtual address
space 0 (Q1)
CS0 memory
space
SDRC registers
SMS registers
MPU global
address space
*
0xFFFF FFFF
0xE000 0000
0xBFFF FFFF
0xA000 0000
0x6D00 0000
0x7000 0000
0x0000 0000
0x8000 0000
0x6C00 0000
0x9FFF FFFF
0x6DFF FFFF
0x7FFF FFFF
0x6CFF FFFF
256 MB
1 GB
4 GB
512 MB
CS1 memory
space
SDRAM 0 (CS0)
256 MB
SDRAM 1 (CS1)
512 MB
* Internal physical address, from a SW point of vue
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SDRAM Controller (SDRC) Subsystem
10.2.6.3 Understanding SDRAM Subsystem Address Spaces
10.2.6.3.1 Physical vs Virtual Address Spaces
One thing that the SMS does is to translate virtual addresses into physical SDRAM addresses in case of
rotation only; that is, when accessing virtual address space 0 (quarter 1) and virtual address space 1
(quarter 3) as shown in
. The SMS then reinserts a request, or multiple requests depending
on the SMS parameters, in the SMS request path to the SDRC controller (through the VRFB or not).
The SDRAM subsytem global memory space mapping reaches 1.768G-bytes:
•
1G-byte of CS memory space (CS0 and CS1 memory spaces): the SDRC controller automatically
accesses the two external memory devices through direct accesses (addresses are simply translated).
•
768M-bytes of virtual address space (address space 0 and address space 1): the SDRC controller
automatically accesses the two external memory devices trough re-organized access (requests are
modified accordingly to the context number and rotation angle before address translation). See section
for more information on VRFB contexts and rotation angles.
Figure 10-76. SDRC Address Space in MPU Global Address Space
Configuration register space is detailed in
Table 10-108. SDRC and SMS Configuration Register Space
Module
Start Address
End Address
Total Space
SMS
0x6C00 0000
0x6CFF FFFF
16 MB
SDRC
0x6D00 0000
0x6DFF FFFF
16 MB
10.2.6.3.1.1 Physical Address Space
The physical address space of the SDRC is 1G byte (maximum addressing capability).
The SDRC has a memory device capacity of 16M bits to 2G bits. The smallest granularity of supported
memory device is 16M bits/2M bytes.
2295
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated