Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2296 / 3738

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SDRAM Controller (SDRC) Subsystem
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10.2.6.3.1.2 Virtual Address Space
The SDRC-SMS virtual memory space is a memory space used to access a subset of the SDRC memory
space through the rotation engine (VRFB). The virtual address space size is 768M bytes split into two
parts: the first 256M-byte part is in the second quarter (Q1) of the memory; the second 512M-byte part is
in the fourth quarter (Q3) of the memory. See
Chapter 2 , Memory Mapping, for more information on global
memory mapping.
The VRFB is a rotation engine that:
• Supports rotations of 0, 90, 180, and 270 degrees
• Can handle up to 12 concurrent rotation contexts
The VRFB has therefore 48 different contexts in the virtual address space. Table 10-109 gives the VRFB
address-space memory locations at which the frame buffer object can be accessed. The table summarizes
the virtual addresses of all 48 available image buffer from a global memory space (top level) point of view.
Table 10-109. VRFB Contexts vs Rotation Angle
Context 0° 90° 180° 270°
Number
0 0x7000 0000 0x7100 0000 0x7200 0000 0x7300 0000
1 0x7400 0000 0x7500 0000 0x7600 0000 0x7700 0000
2 0x7800 0000 0x7900 0000 0x7A00 0000 0x7B00 0000
3 0x7C00 0000 0x7D00 0000 0x7E00 0000 0x7F00 0000
4 0xE000 0000 0xE100 0000 0xE200 0000 0xE300 0000
5 0xE400 0000 0xE500 0000 0xE600 0000 0xE700 0000
6 0xE800 0000 0xE900 0000 0xEA00 0000 0xEB00 0000
7 0xEC00 0000 0xED00 0000 0xEE00 0000 0xEF00 0000
8 0xF000 0000 0xF100 0000 0xF200 0000 0xF300 0000
9 0xF400 0000 0xF500 0000 0xF600 0000 0xF700 0000
10 0xF800 0000 0xF900 0000 0xFA00 0000 0xFB00 0000
11 0xFC00 0000 0xFD00 0000 0xFE00 0000 0xFF00 0000
The physical address of a page is calculated with the formula:
Physical address = Physical base a Base address of page (31)
where Physical base address is defined through the SMS_ROT_PHYSICAL_BAn [30:0] PHYSICALBA field
(buffer physical base address on which the rotation occurs), and Base address of page is the address
obtained in the function of the context number and rotation angle, as given in
Table 10-109 .
10.2.6.3.2 CS Memory Spaces
Two SDRC chip-selects (sdrc_ncs0 and sdrc_ncs1) are available to access two external SDRAM
memories.
10.2.6.3.2.1 SDRAM Capacity Calculation
This section aims to explain how to calculate an SDRAM device capacity.
From the following SDRAM characteristics:
• Four banks: BA0 - BA1
• Row addresses: A0 - A12
• Column addresses: A0 - A9
• 16-bit data bus to external memory
First calculate the number of addressable locations:
• Number of address lines: 13 (A0-A12)
• Number of banks address lines: 2 (BA0-BA1)
• Maximum number of rows = 13 (number of address lines used for row decoding)
2296 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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