Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2313 / 3738

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SDRAM Controller (SDRC) Subsystem
Table 10-147. SMS_ROT_SIZEn
Address Offset 0x0000 0184 + (0x0000 0010 * n) Index n = 0 to 11
Physical Address 0x6C00 0184 + (0x0000 0010 * n) Instance SMS
Description This register configures the bank organization for context #n.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IMAGEHEIGHT RESERVED IMAGEWIDTH
Bits Field Name Description Type Reset
31:27 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00
26:16 IMAGEHEIGHT Image height in pixels for context #n RW 0x000
15:11 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00
10:0 IMAGEWIDTH Image width in pixels for context #n RW 0x000
Table 10-148. Register Call Summary for Register SMS_ROT_SIZEn
SDRAM Controller (SDRC) Subsystem
• Rotation Engine : [0] [1] [2]
• VRFB Context Configuration : [3] [4]
• Applicative Use Case and Tips : [5] [6]
• SMS Register Summary : [7]
Table 10-149. SMS_ROT_PHYSICAL_BAn
Address Offset 0x0000 0188 + (0x0000 0010 * n) Index n = 0 to 11
Physical Address 0x6C00 0188 + (0x0000 0010 * n) Instance SMS
Description This register allows to configure the physical base address for context #n.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSICALBA
RESERVED
Bits Field Name Description Type Reset
31 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
30:0 PHYSICALBA Physical base address of the frame buffer for context #n in SDRAM RW 0x00000000
Table 10-150. Register Call Summary for Register SMS_ROT_PHYSICAL_BAn
SDRAM Controller (SDRC) Subsystem
• Rotation Engine : [0]
• VRFB Context Configuration : [1]
• Applicative Use Case and Tips : [2]
• Physical vs Virtual Address Spaces : [3]
• SMS Register Summary : [4]
10.2.8 SDRC Register Manual
10.2.8.1 SDRC Instance Summary
Table 10-151 gives some details on the SDRC module instance.
2313 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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