DSS
L3 interconnect
L4-Core
L4-PER
L4-EMU
MAD2D
SAD2D
SGX
USBHS
OTG
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Host
USBHS
OTG
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L3 Interconnect
9.2
L3 Interconnect
This section describes the L3 interconnect and its components. With the exception of register points, each
component includes functionality for both the request and response network.
9.2.1 Overview
The L3 interconnect links cores in a flexible topology that couples low power with high performance.
Innovative physical structures and advanced protocols ensure bandwidth and latency to individual IP
cores, providing dedicated connections between IP cores and logical connections over a shared
interconnect.
shows the L3 interconnect.
Figure 9-2. L3 Interconnect Overview
The following are the main features of the L3 interconnect:
•
64-bit multipath interconnect to eliminate on-chip bottlenecks
•
Special internal target for access to L3 registers (RT)
•
Guaranteed quality of service for real-time hardware operators, while maintaining optimal memory
latency for MPU accesses to memory resources
•
True little-endian platform
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Transaction error tracking and logging
•
Built-in protection features:
–
Allow access only to authorized initiator
–
Distributed region-based firewalls for system resource sharing and protection management
•
Signaling support for chip-level power management infrastructure
•
Two interrupt line signaling transaction error
2001
SWPU177N – December 2009 – Revised November 2010
Interconnect
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