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General-Purpose Interface Register Manual
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25.6 General-Purpose Interface Register Manual
This section summarizes the hardware interface for the GPIO product. Each module instance within the
design is shown, together with the module register map and bit definitions for each bit field.
lists the base address and address space for GPIO instances.
Table 25-6. Instance Summary
Module Name
Base Address
Size
GPIO1
0x4831 0000
4KB
GPIO2
0x4905 0000
4KB
GPIO3
0x4905 2000
4KB
GPIO4
0x4905 4000
4KB
GPIO5
0x4905 6000
4KB
GPIO6
0x4905 8000
4KB
25.6.1 General-Purpose Interface Register Mapping Summary
All module registers are 8-, 16-, or 32-bit accessible through the L4 interconnect (little endian encoding).
Access to registers is direct; no shadow registers are implemented.
through
describe the GPIO register offset addresses.
Table 25-7. GPIO1 Register Summary
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
R
32
0x000
0x4831 0000
RW
32
0x010
0x4831 0010
R
32
0x014
0x4831 0014
RW
32
0x018
0x4831 0018
RW
32
0x01C
0x4831 001C
RW
32
0x020
0x4831 0020
RW
32
0x028
0x4831 0028
RW
32
0x02C
0x4831 002C
RW
32
0x030
0x4831 0030
RW
32
0x034
0x4831 0034
R
32
0x038
0x4831 0038
RW
32
0x03C
0x4831 003C
RW
32
0x040
0x4831 0040
RW
32
0x044
0x4831 0044
RW
32
0x048
0x4831 0048
RW
32
0x04C
0x4831 004C
RW
32
0x050
0x4831 0050
RW
32
0x054
0x4831 0054
RW
32
0x060
0x4831 0060
RW
32
0x064
0x4831 0064
RW
32
0x070
0x4831 0070
RW
32
0x074
0x4831 0074
RW
32
0x080
0x4831 0080
RW
32
0x084
0x4831 0084
RW
32
0x090
0x4831 0090
RW
32
0x094
0x4831 0094
3486
General-Purpose Interface
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated