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Camera ISP Basic Programming Model
NOTE:
The granularity for the resizer, HIST, and preview is 32.
6.5.12 Programming the Circular Buffer
6.5.12.1 Camera ISP CBUFF Setup/Initialization
This section discusses the configuration of the circular buffer required before address translation can
begin.
6.5.12.2 Camera ISP CBUFF Reset Behavior
Upon hardware reset of the circular buffer, all of the registers in the circular buffer are reset to their reset
values.
6.5.12.3 Camera ISP CBUFF Register Setup
All registers of the circular buffer to be used (CBUFFx, x=0 or 1) have to be initialized for correct
operation.
The
and
register define the virtual address range managed by the
circular buffer. It usually corresponds to the address region where one image frame is written by the
camera ISP.
The window count and size are set through the
[9:8] WCOUNT and
registers. The window size usually depends on the utilization of the buffer. 8 or
16 video lines correspond to a current size for JPEG video compression. A higher window count provides
better latency related overflow protection.
When the camera ISP accesses data in an incremental addressing scheme, the next window is never
used. In this case the overflow event generation, when the processor window falls into the "next window",
can be disabled by setting the
[3] ALLOW_NW_EQ_CPUW flag.
When the 2D addressing capability is not used the
register is set to the window
size. Otherwise it is set to a smaller value depending on the buffer organization. For example, when each
window corresponds to 8 lines by 4096 pixel but the camera ISP only send lines of 2560 pixels the
=8*4096 and
When the register setup is completed the module is enabled using the
[0] EN bit.
It can be disabled by clearing the
[0] EN bit. This must only be done when there are no
more outstanding requests to the virtual space managed by CBUFFx. All internal FSMs and counters of
the circular buffer are reset when it is disabled. Pending interrupts are not affected.
6.5.12.4 Camera ISP CBUFF Event and status Checking
6.5.12.4.1 Camera ISP CBUFF Interrupts
All events generated by the circular buffer are mapped to an unique event at camera ISP level:
CBUFF_IRQ,
The CBUFF module event can be mapped to the MPU SS or to the IVA SS.
The CBUFF_IRQ bit in the
[21] CBUFF_IRQ register control whether the CBUFF
module event triggers an interrupt to the MPU SS. The CBUFF_IRQ bit in the
[21]
CBUFF_IRQ register control whether the CBUFF module event triggers an interrupt to the IVA2.2 SS.
When an event has been triggered the
[21] CBUFF_IRQ bit is set (or
). SW must than read the
register to know which circular buffer
event has triggered the interrupt. SW must clear the event first in the circular buffer module by writing 1 to
the proper bit in
register and then clear the event at camera ISP level by writing 1 to
the
[21] CBUFF_IRQ bit (or
). If another event is pending at circular
buffer level, the CBUFF_IRQ interrupt is triggered again.
1299
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated
