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Camera ISP Register Manual
Bits
Field Name
Description
Type
Reset
31:0
RESERVED
Write 0s for future compatibility. Reads return zero.
RW
0x00000000
Table 6-122. Register Call Summary for Register CBUFF_SYSCONFIG
Camera ISP Register Manual
•
Camera ISP CBUFF Register Summary
Table 6-123. CBUFF_SYSSTATUS
Address Offset
0x0000 0014
Physical Address
0x480B C114
Instance
ISP_CBUFF
Description
The register provides status information about the module, excluding the interrupt status information
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
Bits
Field Name
Description
Type
Reset
31:0
RESERVED
Reserved for module-specific status information. Reads
R
0x00000000
return 0
Table 6-124. Register Call Summary for Register CBUFF_SYSSTATUS
Camera ISP Register Manual
•
Camera ISP CBUFF Register Summary
Table 6-125. CBUFF_IRQSTATUS
Address Offset
0x0000 0018
Physical Address
0x480B C118
Instance
ISP_CBUFF
Description
The interrupt status register regroups all the status of the module internal events that can generate an
interrupt.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
IRQ_CBUFF1_OVR
IRQ_CBUFF0_OVR
IRQ_CBUFF1_READY
IRQ_CBUFF0_READY
IRQ_CBUFF1_INVALID
IRQ_CBUFF0_INVALID
Bits
Field Name
Description
Type
Reset
31:6
RESERVED
Write 0s for future compatibility. Reads return zero.
RW
0x0000000
5
IRQ_CBUFF1_OVR
Buffer overflow event.
R/W/1to
0x0
Clr
0x0: No done interrupt pending (r); Status unchanged
(w).
0x1: Done interrupt pending (r); Status bit cleared (w).
4
IRQ_CBUFF1_INVALID
Invalid access.
R/W/1to
0x0
Clr
0x0: No done interrupt pending (r); Status unchanged
(w).
0x1: Done interrupt pending (r); Status bit cleared (w).
1331
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated
